drm/i915: Add RPL-U sub platform
Separate out RPLU device ids and add them to both RPL and newly created RPL-U subplatforms. v2: (Matt) - Sort PCI-IDs numerically - Name the sub-platform to accurately depict what it is for - Make RPL-U part of RPL subplatform v3: revert to RPL-U subplatform (Jani) v4: (Jani) - Add RPL-U ids to RPL-P platform - Remove redundant comment Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230130100806.1373883-2-chaitanya.kumar.borah@intel.com
This commit is contained in:
parent
c50ad291e4
commit
61b795a9c3
|
@ -580,6 +580,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
|
|||
IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
|
||||
#define IS_ADLP_RPLP(dev_priv) \
|
||||
IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
|
||||
#define IS_ADLP_RPLU(dev_priv) \
|
||||
IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)
|
||||
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
|
||||
(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
|
||||
#define IS_BDW_ULT(dev_priv) \
|
||||
|
|
|
@ -207,6 +207,10 @@ static const u16 subplatform_rpl_ids[] = {
|
|||
INTEL_RPLP_IDS(0),
|
||||
};
|
||||
|
||||
static const u16 subplatform_rplu_ids[] = {
|
||||
INTEL_RPLU_IDS(0),
|
||||
};
|
||||
|
||||
static const u16 subplatform_g10_ids[] = {
|
||||
INTEL_DG2_G10_IDS(0),
|
||||
INTEL_ATS_M150_IDS(0),
|
||||
|
@ -274,6 +278,9 @@ static void intel_device_info_subplatform_init(struct drm_i915_private *i915)
|
|||
} else if (find_devid(devid, subplatform_rpl_ids,
|
||||
ARRAY_SIZE(subplatform_rpl_ids))) {
|
||||
mask = BIT(INTEL_SUBPLATFORM_RPL);
|
||||
if (find_devid(devid, subplatform_rplu_ids,
|
||||
ARRAY_SIZE(subplatform_rplu_ids)))
|
||||
mask |= BIT(INTEL_SUBPLATFORM_RPLU);
|
||||
} else if (find_devid(devid, subplatform_g10_ids,
|
||||
ARRAY_SIZE(subplatform_g10_ids))) {
|
||||
mask = BIT(INTEL_SUBPLATFORM_G10);
|
||||
|
|
|
@ -127,6 +127,7 @@ enum intel_platform {
|
|||
* bit set
|
||||
*/
|
||||
#define INTEL_SUBPLATFORM_N 1
|
||||
#define INTEL_SUBPLATFORM_RPLU 2
|
||||
|
||||
/* MTL */
|
||||
#define INTEL_SUBPLATFORM_M 0
|
||||
|
|
|
@ -685,14 +685,18 @@
|
|||
INTEL_VGA_DEVICE(0xA78A, info), \
|
||||
INTEL_VGA_DEVICE(0xA78B, info)
|
||||
|
||||
/* RPL-U */
|
||||
#define INTEL_RPLU_IDS(info) \
|
||||
INTEL_VGA_DEVICE(0xA721, info), \
|
||||
INTEL_VGA_DEVICE(0xA7A1, info), \
|
||||
INTEL_VGA_DEVICE(0xA7A9, info)
|
||||
|
||||
/* RPL-P */
|
||||
#define INTEL_RPLP_IDS(info) \
|
||||
INTEL_RPLU_IDS(info), \
|
||||
INTEL_VGA_DEVICE(0xA720, info), \
|
||||
INTEL_VGA_DEVICE(0xA721, info), \
|
||||
INTEL_VGA_DEVICE(0xA7A0, info), \
|
||||
INTEL_VGA_DEVICE(0xA7A1, info), \
|
||||
INTEL_VGA_DEVICE(0xA7A8, info), \
|
||||
INTEL_VGA_DEVICE(0xA7A9, info)
|
||||
INTEL_VGA_DEVICE(0xA7A8, info)
|
||||
|
||||
/* DG2 */
|
||||
#define INTEL_DG2_G10_IDS(info) \
|
||||
|
|
Loading…
Reference in New Issue