riscv: hwprobe: export Zihintpause ISA extension
Export the Zihintpause ISA extension through hwprobe which allows using "pause" instructions. Some userspace applications (OpenJDK for instance) uses this to handle some locking back-off. Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Link: https://lore.kernel.org/r/20240221083108.1235311-1-cleger@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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@ -188,6 +188,10 @@ The following keys are defined:
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manual starting from commit 95cf1f9 ("Add changes requested by Ved
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manual starting from commit 95cf1f9 ("Add changes requested by Ved
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during signoff")
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during signoff")
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* :c:macro:`RISCV_HWPROBE_EXT_ZIHINTPAUSE`: The Zihintpause extension is
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supported as defined in the RISC-V ISA manual starting from commit
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d8ab5c78c207 ("Zihintpause is ratified").
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* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
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* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
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information about the selected set of processors.
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information about the selected set of processors.
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@ -59,6 +59,7 @@ struct riscv_hwprobe {
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#define RISCV_HWPROBE_EXT_ZTSO (1ULL << 33)
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#define RISCV_HWPROBE_EXT_ZTSO (1ULL << 33)
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#define RISCV_HWPROBE_EXT_ZACAS (1ULL << 34)
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#define RISCV_HWPROBE_EXT_ZACAS (1ULL << 34)
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#define RISCV_HWPROBE_EXT_ZICOND (1ULL << 35)
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#define RISCV_HWPROBE_EXT_ZICOND (1ULL << 35)
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#define RISCV_HWPROBE_EXT_ZIHINTPAUSE (1ULL << 36)
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#define RISCV_HWPROBE_KEY_CPUPERF_0 5
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#define RISCV_HWPROBE_KEY_CPUPERF_0 5
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#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
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#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
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#define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
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#define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
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@ -111,6 +111,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
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EXT_KEY(ZTSO);
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EXT_KEY(ZTSO);
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EXT_KEY(ZACAS);
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EXT_KEY(ZACAS);
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EXT_KEY(ZICOND);
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EXT_KEY(ZICOND);
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EXT_KEY(ZIHINTPAUSE);
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if (has_vector()) {
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if (has_vector()) {
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EXT_KEY(ZVBB);
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EXT_KEY(ZVBB);
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