sl82c105: program DMA/PIO timings in ->dma_start/->ide_dma_end
* Program DMA timings in sl82c105_dma_start() (->dma_start method) before starting DMA transfer. * Add sl82c105_dma_end() (->ide_dma_end method) to switch back to PIO timings when DMA transfer is complete. * In sl82c105_set_pio_mode() program timings regardless of ->using_dma setting and in sl82c105_set_dma_mode() only cache the new timings. * Remove no longer needed sl82c105_{ide_dma_on,off_quietly}(). Acked-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
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@ -13,6 +13,7 @@
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* -- Benjamin Herrenschmidt (01/11/03) benh@kernel.crashing.org
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* -- Benjamin Herrenschmidt (01/11/03) benh@kernel.crashing.org
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*
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*
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* Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
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* Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
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* Copyright (C) 2007 Bartlomiej Zolnierkiewicz
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*/
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*/
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#include <linux/types.h>
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#include <linux/types.h>
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@ -90,14 +91,8 @@ static void sl82c105_set_pio_mode(ide_drive_t *drive, const u8 pio)
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drive->drive_data &= 0xffff0000;
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drive->drive_data &= 0xffff0000;
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drive->drive_data |= drv_ctrl;
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drive->drive_data |= drv_ctrl;
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if (!drive->using_dma) {
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pci_write_config_word(dev, reg, drv_ctrl);
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/*
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pci_read_config_word (dev, reg, &drv_ctrl);
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* If we are actually using MW DMA, then we can not
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* reprogram the interface drive control register.
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*/
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pci_write_config_word(dev, reg, drv_ctrl);
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pci_read_config_word (dev, reg, &drv_ctrl);
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}
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printk(KERN_DEBUG "%s: selected %s (%dns) (%04X)\n", drive->name,
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printk(KERN_DEBUG "%s: selected %s (%dns) (%04X)\n", drive->name,
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ide_xfer_verbose(pio + XFER_PIO_0),
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ide_xfer_verbose(pio + XFER_PIO_0),
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@ -123,17 +118,6 @@ static void sl82c105_set_dma_mode(ide_drive_t *drive, const u8 speed)
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*/
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*/
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drive->drive_data &= 0x0000ffff;
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drive->drive_data &= 0x0000ffff;
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drive->drive_data |= (unsigned long)drv_ctrl << 16;
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drive->drive_data |= (unsigned long)drv_ctrl << 16;
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/*
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* If we are already using DMA, we just reprogram
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* the drive control register.
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*/
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if (drive->using_dma) {
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struct pci_dev *dev = HWIF(drive)->pci_dev;
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int reg = 0x44 + drive->dn * 4;
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pci_write_config_word(dev, reg, drv_ctrl);
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}
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}
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}
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/*
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/*
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@ -201,6 +185,11 @@ static void sl82c105_dma_start(ide_drive_t *drive)
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{
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{
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ide_hwif_t *hwif = HWIF(drive);
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ide_hwif_t *hwif = HWIF(drive);
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struct pci_dev *dev = hwif->pci_dev;
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struct pci_dev *dev = hwif->pci_dev;
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int reg = 0x44 + drive->dn * 4;
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DBG(("%s(drive:%s)\n", __FUNCTION__, drive->name));
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pci_write_config_word(dev, reg, drive->drive_data >> 16);
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sl82c105_reset_host(dev);
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sl82c105_reset_host(dev);
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ide_dma_start(drive);
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ide_dma_start(drive);
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@ -214,32 +203,19 @@ static void sl82c105_dma_timeout(ide_drive_t *drive)
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ide_dma_timeout(drive);
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ide_dma_timeout(drive);
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}
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}
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static int sl82c105_ide_dma_on(ide_drive_t *drive)
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static int sl82c105_dma_end(ide_drive_t *drive)
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{
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struct pci_dev *dev = HWIF(drive)->pci_dev;
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int rc, reg = 0x44 + drive->dn * 4;
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DBG(("sl82c105_ide_dma_on(drive:%s)\n", drive->name));
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rc = __ide_dma_on(drive);
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if (rc == 0) {
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pci_write_config_word(dev, reg, drive->drive_data >> 16);
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printk(KERN_INFO "%s: DMA enabled\n", drive->name);
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}
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return rc;
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}
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static void sl82c105_dma_off_quietly(ide_drive_t *drive)
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{
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{
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struct pci_dev *dev = HWIF(drive)->pci_dev;
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struct pci_dev *dev = HWIF(drive)->pci_dev;
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int reg = 0x44 + drive->dn * 4;
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int reg = 0x44 + drive->dn * 4;
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int ret;
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DBG(("sl82c105_dma_off_quietly(drive:%s)\n", drive->name));
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DBG(("%s(drive:%s)\n", __FUNCTION__, drive->name));
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ret = __ide_dma_end(drive);
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pci_write_config_word(dev, reg, drive->drive_data);
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pci_write_config_word(dev, reg, drive->drive_data);
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ide_dma_off_quietly(drive);
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return ret;
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}
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}
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/*
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/*
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@ -369,10 +345,9 @@ static void __devinit init_hwif_sl82c105(ide_hwif_t *hwif)
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hwif->mwdma_mask = ATA_MWDMA2;
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hwif->mwdma_mask = ATA_MWDMA2;
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hwif->ide_dma_on = &sl82c105_ide_dma_on;
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hwif->dma_off_quietly = &sl82c105_dma_off_quietly;
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hwif->dma_lost_irq = &sl82c105_dma_lost_irq;
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hwif->dma_lost_irq = &sl82c105_dma_lost_irq;
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hwif->dma_start = &sl82c105_dma_start;
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hwif->dma_start = &sl82c105_dma_start;
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hwif->ide_dma_end = &sl82c105_dma_end;
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hwif->dma_timeout = &sl82c105_dma_timeout;
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hwif->dma_timeout = &sl82c105_dma_timeout;
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if (hwif->mate)
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if (hwif->mate)
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