riscv: add support for misaligned trap handling in S-mode
Misalignment trap handling is only supported for M-mode and uses direct accesses to user memory. In S-mode, when handling usermode fault, this requires to use the get_user()/put_user() accessors. Implement load_u8(), store_u8() and get_insn() using these accessors for userspace and direct text access for kernel. Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Björn Töpel <bjorn@rivosinc.com> Link: https://lore.kernel.org/r/20231004151405.521596-3-cleger@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
This commit is contained in:
Clément Léger
Palmer Dabbelt
parent
f19c3b4239
commit
7c83232161
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@ -636,6 +636,14 @@ config THREAD_SIZE_ORDER
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Specify the Pages of thread stack size (from 4KB to 64KB), which also
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affects irq stack size, which is equal to thread stack size.
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config RISCV_MISALIGNED
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bool "Support misaligned load/store traps for kernel and userspace"
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default y
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help
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Say Y here if you want the kernel to embed support for misaligned
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load/store for both kernel and userspace. When disable, misaligned
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accesses will generate SIGBUS in userspace and panic in kernel.
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endmenu # "Platform type"
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menu "Kernel features"
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@ -8,4 +8,18 @@
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void handle_page_fault(struct pt_regs *regs);
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void handle_break(struct pt_regs *regs);
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#ifdef CONFIG_RISCV_MISALIGNED
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int handle_misaligned_load(struct pt_regs *regs);
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int handle_misaligned_store(struct pt_regs *regs);
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#else
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static inline int handle_misaligned_load(struct pt_regs *regs)
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{
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return -1;
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}
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static inline int handle_misaligned_store(struct pt_regs *regs)
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{
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return -1;
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}
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#endif
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#endif /* _ASM_RISCV_ENTRY_COMMON_H */
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@ -59,7 +59,7 @@ obj-y += patch.o
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obj-y += probes/
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obj-$(CONFIG_MMU) += vdso.o vdso/
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obj-$(CONFIG_RISCV_M_MODE) += traps_misaligned.o
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obj-$(CONFIG_RISCV_MISALIGNED) += traps_misaligned.o
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obj-$(CONFIG_FPU) += fpu.o
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obj-$(CONFIG_RISCV_ISA_V) += vector.o
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obj-$(CONFIG_SMP) += smpboot.o
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@ -179,14 +179,6 @@ asmlinkage __visible __trap_section void do_trap_insn_illegal(struct pt_regs *re
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DO_ERROR_INFO(do_trap_load_fault,
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SIGSEGV, SEGV_ACCERR, "load access fault");
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#ifndef CONFIG_RISCV_M_MODE
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DO_ERROR_INFO(do_trap_load_misaligned,
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SIGBUS, BUS_ADRALN, "Oops - load address misaligned");
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DO_ERROR_INFO(do_trap_store_misaligned,
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SIGBUS, BUS_ADRALN, "Oops - store (or AMO) address misaligned");
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#else
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int handle_misaligned_load(struct pt_regs *regs);
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int handle_misaligned_store(struct pt_regs *regs);
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asmlinkage __visible __trap_section void do_trap_load_misaligned(struct pt_regs *regs)
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{
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@ -229,7 +221,6 @@ asmlinkage __visible __trap_section void do_trap_store_misaligned(struct pt_regs
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irqentry_nmi_exit(regs, state);
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}
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}
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#endif
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DO_ERROR_INFO(do_trap_store_fault,
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SIGSEGV, SEGV_ACCERR, "store (or AMO) access fault");
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DO_ERROR_INFO(do_trap_ecall_s,
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@ -12,6 +12,7 @@
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#include <asm/processor.h>
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#include <asm/ptrace.h>
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#include <asm/csr.h>
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#include <asm/entry-common.h>
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#define INSN_MATCH_LB 0x3
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#define INSN_MASK_LB 0x707f
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@ -151,21 +152,25 @@
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#define PRECISION_S 0
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#define PRECISION_D 1
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static inline u8 load_u8(const u8 *addr)
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#ifdef CONFIG_RISCV_M_MODE
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static inline int load_u8(struct pt_regs *regs, const u8 *addr, u8 *r_val)
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{
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u8 val;
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asm volatile("lbu %0, %1" : "=&r" (val) : "m" (*addr));
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*r_val = val;
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return val;
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return 0;
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}
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static inline void store_u8(u8 *addr, u8 val)
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static inline int store_u8(struct pt_regs *regs, u8 *addr, u8 val)
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{
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asm volatile ("sb %0, %1\n" : : "r" (val), "m" (*addr));
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return 0;
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}
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static inline ulong get_insn(ulong mepc)
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static inline int get_insn(struct pt_regs *regs, ulong mepc, ulong *r_insn)
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{
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register ulong __mepc asm ("a2") = mepc;
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ulong val, rvc_mask = 3, tmp;
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@ -194,8 +199,86 @@ static inline ulong get_insn(ulong mepc)
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: [addr] "r" (__mepc), [rvc_mask] "r" (rvc_mask),
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[xlen_minus_16] "i" (XLEN_MINUS_16));
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return val;
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*r_insn = val;
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return 0;
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}
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#else
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static inline int load_u8(struct pt_regs *regs, const u8 *addr, u8 *r_val)
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{
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if (user_mode(regs)) {
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return __get_user(*r_val, addr);
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} else {
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*r_val = *addr;
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return 0;
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}
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}
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static inline int store_u8(struct pt_regs *regs, u8 *addr, u8 val)
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{
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if (user_mode(regs)) {
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return __put_user(val, addr);
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} else {
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*addr = val;
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return 0;
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}
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}
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#define __read_insn(regs, insn, insn_addr) \
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({ \
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int __ret; \
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\
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if (user_mode(regs)) { \
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__ret = __get_user(insn, insn_addr); \
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} else { \
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insn = *insn_addr; \
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__ret = 0; \
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} \
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\
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__ret; \
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})
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static inline int get_insn(struct pt_regs *regs, ulong epc, ulong *r_insn)
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{
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ulong insn = 0;
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if (epc & 0x2) {
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ulong tmp = 0;
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u16 __user *insn_addr = (u16 __user *)epc;
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if (__read_insn(regs, insn, insn_addr))
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return -EFAULT;
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/* __get_user() uses regular "lw" which sign extend the loaded
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* value make sure to clear higher order bits in case we "or" it
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* below with the upper 16 bits half.
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*/
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insn &= GENMASK(15, 0);
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if ((insn & __INSN_LENGTH_MASK) != __INSN_LENGTH_32) {
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*r_insn = insn;
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return 0;
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}
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insn_addr++;
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if (__read_insn(regs, tmp, insn_addr))
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return -EFAULT;
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*r_insn = (tmp << 16) | insn;
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return 0;
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} else {
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u32 __user *insn_addr = (u32 __user *)epc;
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if (__read_insn(regs, insn, insn_addr))
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return -EFAULT;
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if ((insn & __INSN_LENGTH_MASK) == __INSN_LENGTH_32) {
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*r_insn = insn;
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return 0;
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}
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insn &= GENMASK(15, 0);
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*r_insn = insn;
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return 0;
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}
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}
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#endif
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union reg_data {
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u8 data_bytes[8];
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@ -207,10 +290,13 @@ int handle_misaligned_load(struct pt_regs *regs)
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{
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union reg_data val;
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unsigned long epc = regs->epc;
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unsigned long insn = get_insn(epc);
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unsigned long addr = csr_read(mtval);
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unsigned long insn;
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unsigned long addr = regs->badaddr;
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int i, fp = 0, shift = 0, len = 0;
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if (get_insn(regs, epc, &insn))
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return -1;
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regs->epc = 0;
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if ((insn & INSN_MASK_LW) == INSN_MATCH_LW) {
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@ -274,8 +360,10 @@ int handle_misaligned_load(struct pt_regs *regs)
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}
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val.data_u64 = 0;
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for (i = 0; i < len; i++)
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val.data_bytes[i] = load_u8((void *)(addr + i));
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for (i = 0; i < len; i++) {
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if (load_u8(regs, (void *)(addr + i), &val.data_bytes[i]))
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return -1;
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}
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if (fp)
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return -1;
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@ -290,10 +378,13 @@ int handle_misaligned_store(struct pt_regs *regs)
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{
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union reg_data val;
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unsigned long epc = regs->epc;
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unsigned long insn = get_insn(epc);
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unsigned long addr = csr_read(mtval);
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unsigned long insn;
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unsigned long addr = regs->badaddr;
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int i, len = 0;
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if (get_insn(regs, epc, &insn))
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return -1;
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regs->epc = 0;
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val.data_ulong = GET_RS2(insn, regs);
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@ -327,8 +418,10 @@ int handle_misaligned_store(struct pt_regs *regs)
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return -1;
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}
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for (i = 0; i < len; i++)
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store_u8((void *)(addr + i), val.data_bytes[i]);
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for (i = 0; i < len; i++) {
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if (store_u8(regs, (void *)(addr + i), val.data_bytes[i]))
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return -1;
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}
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regs->epc = epc + INSN_LEN(insn);
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