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arm/arm64: dts: Drop "arm,armv8-pmuv3" compatible usage 

The "arm,armv8-pmuv3" compatible is intended only for s/w models. Primarily,
it doesn't provide any detail on uarch specific events.

There's still remaining cases for CPUs without any corresponding PMU
definition and for big.LITTLE systems which only have a single PMU node
(there should be one per core type).

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Jisheng Zhang <jszhang@kernel.org>
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Acked-by: Dinh Nguyen <dinguyen@kernel.org>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Bjorn Andersson <andersson@kernel.org>
Acked-by: Florian Fainelli <florian.fainelli@broadcom.com>
Acked-by: Alim Akhtar <alim.akhtar@samsung.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Link: https://lore.kernel.org/r/20240417203853.3212103-1-robh@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Rob Herring 2024-04-17 15:38:47 -05:00 committed by Arnd Bergmann
parent f45083c343
commit 8b40a46966
No known key found for this signature in database
GPG Key ID: 60AB47FFC9095227
31 changed files with 43 additions and 34 deletions
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4
arch/arm/boot/dts/broadcom/bcm2711.dtsi
View File

@ -432,8 +432,8 @@
};
};
arm-pmu {
compatible = "arm,cortex-a72-pmu", "arm,armv8-pmuv3";
pmu {
compatible = "arm,cortex-a72-pmu";
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,

2
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
View File

@ -79,7 +79,7 @@
};
pmu {
compatible = "arm,armv8-pmuv3";
compatible = "arm,cortex-a53-pmu";
interrupts = <0 170 4>,
<0 171 4>,
<0 172 4>,

2
arch/arm64/boot/dts/amazon/alpine-v2.dtsi
View File

@ -106,7 +106,7 @@
};
pmu {
compatible = "arm,armv8-pmuv3";
compatible = "arm,cortex-a57-pmu";
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,

2
arch/arm64/boot/dts/apm/apm-storm.dtsi
View File

@ -122,7 +122,7 @@
};
pmu {
compatible = "apm,potenza-pmu", "arm,armv8-pmuv3";
compatible = "apm,potenza-pmu";
interrupts = <1 12 0xff04>;
};

2
arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts
View File

@ -102,7 +102,7 @@
};
pmu {
compatible = "arm,armv8-pmuv3";
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
};

2
arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi
View File

@ -102,7 +102,7 @@
};
pmu {
compatible = "arm,armv8-pmuv3";
compatible = "arm,cortex-a57-pmu";
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

2
arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
View File

@ -142,7 +142,7 @@
};
pmu {
compatible = "arm,armv8-pmuv3";
compatible = "arm,cortex-a72-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};

2
arch/arm64/boot/dts/cavium/thunder-88xx.dtsi
View File

@ -361,7 +361,7 @@
};
pmu {
compatible = "cavium,thunder-pmu", "arm,armv8-pmuv3";
compatible = "cavium,thunder-pmu";
interrupts = <1 7 4>;
};

2
arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi
View File

@ -83,7 +83,7 @@
};
pmu {
compatible = "brcm,vulcan-pmu", "arm,armv8-pmuv3";
compatible = "brcm,vulcan-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; /* PMU overflow */
};

2
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
View File

@ -81,7 +81,7 @@
};
pmu {
compatible = "arm,armv8-pmuv3";
compatible = "arm,cortex-a53-pmu";
interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
};

2
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
View File

@ -276,7 +276,7 @@
};
pmu {
compatible = "arm,armv8-pmuv3";
compatible = "arm,cortex-a53-pmu";
interrupts = <0 106 0x4>,
<0 107 0x4>,
<0 95 0x4>,

7
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
View File

@ -12,6 +12,13 @@
#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
#include "fsl-ls208xa.dtsi"
/ {
pmu {
compatible = "arm,cortex-a57-pmu";
interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
};
};
&cpu {
cpu0: cpu@0 {
device_type = "cpu";

7
arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
View File

@ -12,6 +12,13 @@
#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
#include "fsl-ls208xa.dtsi"
/ {
pmu {
compatible = "arm,cortex-a72-pmu";
interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
};
};
&cpu {
cpu0: cpu@0 {
device_type = "cpu";

5
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
View File

@ -247,11 +247,6 @@
<1 10 4>; /* Hypervisor PPI, active-low */
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
};
psci {
compatible = "arm,psci-0.2";
method = "smc";

2
arch/arm64/boot/dts/freescale/imx8dxl.dtsi
View File

@ -104,7 +104,7 @@
};
pmu {
compatible = "arm,armv8-pmuv3";
compatible = "arm,cortex-a35-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};

2
arch/arm64/boot/dts/intel/keembay-soc.dtsi
View File

@ -70,7 +70,7 @@
};
pmu {
compatible = "arm,armv8-pmuv3";
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 0x7 IRQ_TYPE_LEVEL_HIGH>;
};

2
arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
View File

@ -80,7 +80,7 @@
};
pmu {
compatible = "arm,armv8-pmuv3";
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,

2
arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
View File

@ -68,7 +68,7 @@
};
pmu {
compatible = "arm,armv8-pmuv3";
compatible = "arm,cortex-a55-pmu";
interrupts = <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>;
};

2
arch/arm64/boot/dts/marvell/armada-37xx.dtsi
View File

@ -68,7 +68,7 @@
};
pmu {
compatible = "arm,armv8-pmuv3";
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};

2
arch/arm64/boot/dts/mediatek/mt8516.dtsi
View File

@ -165,7 +165,7 @@
};
pmu {
compatible = "arm,armv8-pmuv3";
compatible = "arm,cortex-a35-pmu";
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_LOW>,

2
arch/arm64/boot/dts/nvidia/tegra210.dtsi
View File

@ -2004,7 +2004,7 @@
};
pmu {
compatible = "arm,armv8-pmuv3";
compatible = "arm,cortex-a57-pmu";
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,

2
arch/arm64/boot/dts/qcom/qcm2290.dtsi
View File

@ -165,7 +165,7 @@
};
pmu {
compatible = "arm,armv8-pmuv3";
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
};

2
arch/arm64/boot/dts/qcom/qdu1000.dtsi
View File

@ -177,7 +177,7 @@
};
pmu {
compatible = "arm,armv8-pmuv3";
compatible = "arm,cortex-a55-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};

2
arch/arm64/boot/dts/qcom/sdx75.dtsi
View File

@ -224,7 +224,7 @@
};
pmu {
compatible = "arm,armv8-pmuv3";
compatible = "arm,cortex-a55-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};

2
arch/arm64/boot/dts/realtek/rtd16xx.dtsi
View File

@ -109,7 +109,7 @@
};
arm_pmu: pmu {
compatible = "arm,armv8-pmuv3";
compatible = "arm,cortex-a55-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>,
<&cpu3>, <&cpu4>, <&cpu5>;

2
arch/arm64/boot/dts/rockchip/rk3368.dtsi
View File

@ -141,7 +141,7 @@
};
arm-pmu {
compatible = "arm,armv8-pmuv3";
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,

2
arch/arm64/boot/dts/sprd/sc9860.dtsi
View File

@ -165,7 +165,7 @@
};
pmu {
compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3";
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,

2
arch/arm64/boot/dts/sprd/sc9863a.dtsi
View File

@ -134,7 +134,7 @@
};
pmu {
compatible = "arm,armv8-pmuv3";
compatible = "arm,cortex-a55-pmu";
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,

2
arch/arm64/boot/dts/synaptics/berlin4ct.dtsi
View File

@ -88,7 +88,7 @@
};
pmu {
compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3";
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,

2
arch/arm64/boot/dts/tesla/fsd.dtsi
View File

@ -304,7 +304,7 @@
};
arm-pmu {
compatible = "arm,armv8-pmuv3";
compatible = "arm,cortex-a72-pmu";
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,

2
arch/arm64/boot/dts/xilinx/zynqmp.dtsi
View File

@ -169,7 +169,7 @@
};
pmu {
compatible = "arm,armv8-pmuv3";
compatible = "arm,cortex-a53-pmu";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,