docs: trace: Add HiSilicon PTT device driver documentation
Document the introduction and usage of HiSilicon PTT device driver as well as the sysfs attributes description provided by the driver. Signed-off-by: Yicong Yang <yangyicong@hisilicon.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Bagas Sanjaya <bagasdotme@gmail.com> [Fixed month and kernel version] Link: https://lore.kernel.org/r/20220816114414.4092-5-yangyicong@huawei.com Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
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Yicong Yang
Mathieu Poirier
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What: /sys/devices/hisi_ptt<sicl_id>_<core_id>/tune
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Date: October 2022
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KernelVersion: 6.1
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Contact: Yicong Yang <yangyicong@hisilicon.com>
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Description: This directory contains files for tuning the PCIe link
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parameters(events). Each file is named after the event
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of the PCIe link.
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See Documentation/trace/hisi-ptt.rst for more information.
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What: /sys/devices/hisi_ptt<sicl_id>_<core_id>/tune/qos_tx_cpl
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Date: October 2022
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KernelVersion: 6.1
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Contact: Yicong Yang <yangyicong@hisilicon.com>
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Description: (RW) Controls the weight of Tx completion TLPs, which influence
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the proportion of outbound completion TLPs on the PCIe link.
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The available tune data is [0, 1, 2]. Writing a negative value
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will return an error, and out of range values will be converted
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to 2. The value indicates a probable level of the event.
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What: /sys/devices/hisi_ptt<sicl_id>_<core_id>/tune/qos_tx_np
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Date: October 2022
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KernelVersion: 6.1
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Contact: Yicong Yang <yangyicong@hisilicon.com>
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Description: (RW) Controls the weight of Tx non-posted TLPs, which influence
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the proportion of outbound non-posted TLPs on the PCIe link.
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The available tune data is [0, 1, 2]. Writing a negative value
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will return an error, and out of range values will be converted
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to 2. The value indicates a probable level of the event.
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What: /sys/devices/hisi_ptt<sicl_id>_<core_id>/tune/qos_tx_p
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Date: October 2022
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KernelVersion: 6.1
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Contact: Yicong Yang <yangyicong@hisilicon.com>
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Description: (RW) Controls the weight of Tx posted TLPs, which influence the
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proportion of outbound posted TLPs on the PCIe link.
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The available tune data is [0, 1, 2]. Writing a negative value
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will return an error, and out of range values will be converted
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to 2. The value indicates a probable level of the event.
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What: /sys/devices/hisi_ptt<sicl_id>_<core_id>/tune/rx_alloc_buf_level
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Date: October 2022
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KernelVersion: 6.1
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Contact: Yicong Yang <yangyicong@hisilicon.com>
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Description: (RW) Control the allocated buffer watermark for inbound packets.
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The packets will be stored in the buffer first and then transmitted
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either when the watermark reached or when timed out.
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The available tune data is [0, 1, 2]. Writing a negative value
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will return an error, and out of range values will be converted
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to 2. The value indicates a probable level of the event.
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What: /sys/devices/hisi_ptt<sicl_id>_<core_id>/tune/tx_alloc_buf_level
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Date: October 2022
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KernelVersion: 6.1
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Contact: Yicong Yang <yangyicong@hisilicon.com>
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Description: (RW) Control the allocated buffer watermark of outbound packets.
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The packets will be stored in the buffer first and then transmitted
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either when the watermark reached or when timed out.
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The available tune data is [0, 1, 2]. Writing a negative value
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will return an error, and out of range values will be converted
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to 2. The value indicates a probable level of the event.
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@ -0,0 +1,298 @@
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.. SPDX-License-Identifier: GPL-2.0
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======================================
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HiSilicon PCIe Tune and Trace device
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======================================
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Introduction
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============
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HiSilicon PCIe tune and trace device (PTT) is a PCIe Root Complex
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integrated Endpoint (RCiEP) device, providing the capability
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to dynamically monitor and tune the PCIe link's events (tune),
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and trace the TLP headers (trace). The two functions are independent,
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but is recommended to use them together to analyze and enhance the
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PCIe link's performance.
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On Kunpeng 930 SoC, the PCIe Root Complex is composed of several
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PCIe cores. Each PCIe core includes several Root Ports and a PTT
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RCiEP, like below. The PTT device is capable of tuning and
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tracing the links of the PCIe core.
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::
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+--------------Core 0-------+
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| | [ PTT ] |
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| | [Root Port]---[Endpoint]
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| | [Root Port]---[Endpoint]
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| | [Root Port]---[Endpoint]
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Root Complex |------Core 1-------+
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| | [ PTT ] |
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| | [Root Port]---[ Switch ]---[Endpoint]
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| | [Root Port]---[Endpoint] `-[Endpoint]
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| | [Root Port]---[Endpoint]
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+---------------------------+
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The PTT device driver registers one PMU device for each PTT device.
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The name of each PTT device is composed of 'hisi_ptt' prefix with
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the id of the SICL and the Core where it locates. The Kunpeng 930
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SoC encapsulates multiple CPU dies (SCCL, Super CPU Cluster) and
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IO dies (SICL, Super I/O Cluster), where there's one PCIe Root
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Complex for each SICL.
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::
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/sys/devices/hisi_ptt<sicl_id>_<core_id>
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Tune
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====
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PTT tune is designed for monitoring and adjusting PCIe link parameters (events).
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Currently we support events in 2 classes. The scope of the events
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covers the PCIe core to which the PTT device belongs.
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Each event is presented as a file under $(PTT PMU dir)/tune, and
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a simple open/read/write/close cycle will be used to tune the event.
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::
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$ cd /sys/devices/hisi_ptt<sicl_id>_<core_id>/tune
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$ ls
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qos_tx_cpl qos_tx_np qos_tx_p
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tx_path_rx_req_alloc_buf_level
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tx_path_tx_req_alloc_buf_level
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$ cat qos_tx_dp
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1
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$ echo 2 > qos_tx_dp
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$ cat qos_tx_dp
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2
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Current value (numerical value) of the event can be simply read
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from the file, and the desired value written to the file to tune.
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1. Tx Path QoS Control
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------------------------
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The following files are provided to tune the QoS of the tx path of
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the PCIe core.
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- qos_tx_cpl: weight of Tx completion TLPs
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- qos_tx_np: weight of Tx non-posted TLPs
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- qos_tx_p: weight of Tx posted TLPs
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The weight influences the proportion of certain packets on the PCIe link.
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For example, for the storage scenario, increase the proportion
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of the completion packets on the link to enhance the performance as
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more completions are consumed.
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The available tune data of these events is [0, 1, 2].
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Writing a negative value will return an error, and out of range
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values will be converted to 2. Note that the event value just
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indicates a probable level, but is not precise.
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2. Tx Path Buffer Control
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-------------------------
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Following files are provided to tune the buffer of tx path of the PCIe core.
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- rx_alloc_buf_level: watermark of Rx requested
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- tx_alloc_buf_level: watermark of Tx requested
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These events influence the watermark of the buffer allocated for each
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type. Rx means the inbound while Tx means outbound. The packets will
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be stored in the buffer first and then transmitted either when the
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watermark reached or when timed out. For a busy direction, you should
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increase the related buffer watermark to avoid frequently posting and
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thus enhance the performance. In most cases just keep the default value.
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The available tune data of above events is [0, 1, 2].
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Writing a negative value will return an error, and out of range
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values will be converted to 2. Note that the event value just
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indicates a probable level, but is not precise.
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Trace
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=====
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PTT trace is designed for dumping the TLP headers to the memory, which
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can be used to analyze the transactions and usage condition of the PCIe
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Link. You can choose to filter the traced headers by either Requester ID,
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or those downstream of a set of Root Ports on the same core of the PTT
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device. It's also supported to trace the headers of certain type and of
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certain direction.
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You can use the perf command `perf record` to set the parameters, start
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trace and get the data. It's also supported to decode the trace
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data with `perf report`. The control parameters for trace is inputted
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as event code for each events, which will be further illustrated later.
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An example usage is like
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::
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$ perf record -e hisi_ptt0_2/filter=0x80001,type=1,direction=1,
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format=1/ -- sleep 5
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This will trace the TLP headers downstream root port 0000:00:10.1 (event
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code for event 'filter' is 0x80001) with type of posted TLP requests,
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direction of inbound and traced data format of 8DW.
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1. Filter
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---------
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The TLP headers to trace can be filtered by the Root Ports or the Requester ID
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of the Endpoint, which are located on the same core of the PTT device. You can
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set the filter by specifying the `filter` parameter which is required to start
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the trace. The parameter value is 20 bit. Bit 19 indicates the filter type.
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1 for Root Port filter and 0 for Requester filter. Bit[15:0] indicates the
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filter value. The value for a Root Port is a mask of the core port id which is
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calculated from its PCI Slot ID as (slotid & 7) * 2. The value for a Requester
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is the Requester ID (Device ID of the PCIe function). Bit[18:16] is currently
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reserved for extension.
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For example, if the desired filter is Endpoint function 0000:01:00.1 the filter
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value will be 0x00101. If the desired filter is Root Port 0000:00:10.0 then
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then filter value is calculated as 0x80001.
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Note that multiple Root Ports can be specified at one time, but only one
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Endpoint function can be specified in one trace. Specifying both Root Port
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and function at the same time is not supported. Driver maintains a list of
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available filters and will check the invalid inputs.
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Currently the available filters are detected in driver's probe. If the supported
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devices are removed/added after probe, you may need to reload the driver to update
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the filters.
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2. Type
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-------
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You can trace the TLP headers of certain types by specifying the `type`
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parameter, which is required to start the trace. The parameter value is
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8 bit. Current supported types and related values are shown below:
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- 8'b00000001: posted requests (P)
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- 8'b00000010: non-posted requests (NP)
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- 8'b00000100: completions (CPL)
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You can specify multiple types when tracing inbound TLP headers, but can only
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specify one when tracing outbound TLP headers.
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3. Direction
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------------
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You can trace the TLP headers from certain direction, which is relative
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to the Root Port or the PCIe core, by specifying the `direction` parameter.
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This is optional and the default parameter is inbound. The parameter value
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is 4 bit. When the desired format is 4DW, directions and related values
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supported are shown below:
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- 4'b0000: inbound TLPs (P, NP, CPL)
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- 4'b0001: outbound TLPs (P, NP, CPL)
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- 4'b0010: outbound TLPs (P, NP, CPL) and inbound TLPs (P, NP, CPL B)
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- 4'b0011: outbound TLPs (P, NP, CPL) and inbound TLPs (CPL A)
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When the desired format is 8DW, directions and related values supported are
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shown below:
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- 4'b0000: reserved
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- 4'b0001: outbound TLPs (P, NP, CPL)
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- 4'b0010: inbound TLPs (P, NP, CPL B)
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- 4'b0011: inbound TLPs (CPL A)
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Inbound completions are classified into two types:
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- completion A (CPL A): completion of CHI/DMA/Native non-posted requests, except for CPL B
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- completion B (CPL B): completion of DMA remote2local and P2P non-posted requests
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4. Format
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--------------
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You can change the format of the traced TLP headers by specifying the
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`format` parameter. The default format is 4DW. The parameter value is 4 bit.
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Current supported formats and related values are shown below:
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- 4'b0000: 4DW length per TLP header
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- 4'b0001: 8DW length per TLP header
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The traced TLP header format is different from the PCIe standard.
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When using the 8DW data format, the entire TLP header is logged
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(Header DW0-3 shown below). For example, the TLP header for Memory
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Reads with 64-bit addresses is shown in PCIe r5.0, Figure 2-17;
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the header for Configuration Requests is shown in Figure 2.20, etc.
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In addition, 8DW trace buffer entries contain a timestamp and
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possibly a prefix for a PASID TLP prefix (see Figure 6-20, PCIe r5.0).
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Otherwise this field will be all 0.
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The bit[31:11] of DW0 is always 0x1fffff, which can be
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used to distinguish the data format. 8DW format is like
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::
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bits [ 31:11 ][ 10:0 ]
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|---------------------------------------|-------------------|
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DW0 [ 0x1fffff ][ Reserved (0x7ff) ]
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DW1 [ Prefix ]
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DW2 [ Header DW0 ]
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DW3 [ Header DW1 ]
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DW4 [ Header DW2 ]
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DW5 [ Header DW3 ]
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DW6 [ Reserved (0x0) ]
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DW7 [ Time ]
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When using the 4DW data format, DW0 of the trace buffer entry
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contains selected fields of DW0 of the TLP, together with a
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timestamp. DW1-DW3 of the trace buffer entry contain DW1-DW3
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directly from the TLP header.
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4DW format is like
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::
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bits [31:30] [ 29:25 ][24][23][22][21][ 20:11 ][ 10:0 ]
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|-----|---------|---|---|---|---|-------------|-------------|
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DW0 [ Fmt ][ Type ][T9][T8][TH][SO][ Length ][ Time ]
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DW1 [ Header DW1 ]
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DW2 [ Header DW2 ]
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DW3 [ Header DW3 ]
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5. Memory Management
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--------------------
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The traced TLP headers will be written to the memory allocated
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by the driver. The hardware accepts 4 DMA address with same size,
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and writes the buffer sequentially like below. If DMA addr 3 is
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finished and the trace is still on, it will return to addr 0.
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::
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+->[DMA addr 0]->[DMA addr 1]->[DMA addr 2]->[DMA addr 3]-+
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+---------------------------------------------------------+
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Driver will allocate each DMA buffer of 4MiB. The finished buffer
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will be copied to the perf AUX buffer allocated by the perf core.
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Once the AUX buffer is full while the trace is still on, driver
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will commit the AUX buffer first and then apply for a new one with
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the same size. The size of AUX buffer is default to 16MiB. User can
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adjust the size by specifying the `-m` parameter of the perf command.
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6. Decoding
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-----------
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You can decode the traced data with `perf report -D` command (currently
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only support to dump the raw trace data). The traced data will be decoded
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according to the format described previously (take 8DW as an example):
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::
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[...perf headers and other information]
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. ... HISI PTT data: size 4194304 bytes
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. 00000000: 00 00 00 00 Prefix
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. 00000004: 01 00 00 60 Header DW0
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. 00000008: 0f 1e 00 01 Header DW1
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. 0000000c: 04 00 00 00 Header DW2
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. 00000010: 40 00 81 02 Header DW3
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. 00000014: 33 c0 04 00 Time
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. 00000020: 00 00 00 00 Prefix
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. 00000024: 01 00 00 60 Header DW0
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. 00000028: 0f 1e 00 01 Header DW1
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. 0000002c: 04 00 00 00 Header DW2
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. 00000030: 40 00 81 02 Header DW3
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. 00000034: 02 00 00 00 Time
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. 00000040: 00 00 00 00 Prefix
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. 00000044: 01 00 00 60 Header DW0
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. 00000048: 0f 1e 00 01 Header DW1
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. 0000004c: 04 00 00 00 Header DW2
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. 00000050: 40 00 81 02 Header DW3
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[...]
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@ -33,3 +33,4 @@ Linux Tracing Technologies
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coresight/index
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user_events
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rv/index
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hisi-ptt
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