powerpc/mm/radix: Add radix pte #defines
This adds Power ISA 3.0 specific pte defines. We share most of the details with hash Linux page table format. This patch indicates only things where we differ. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Aneesh Kumar K.V
Michael Ellerman
parent
34fbadd8e9
commit
b0b5e9b130
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@ -205,6 +205,7 @@ extern unsigned long __pgd_table_size;
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#endif /* __ASSEMBLY__ */
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#include <asm/book3s/64/hash.h>
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#include <asm/book3s/64/radix.h>
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#include <asm/barrier.h>
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/*
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@ -0,0 +1,12 @@
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#ifndef _ASM_POWERPC_PGTABLE_RADIX_4K_H
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#define _ASM_POWERPC_PGTABLE_RADIX_4K_H
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/*
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* For 4K page size supported index is 13/9/9/9
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*/
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#define RADIX_PTE_INDEX_SIZE 9 /* 2MB huge page */
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#define RADIX_PMD_INDEX_SIZE 9 /* 1G huge page */
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#define RADIX_PUD_INDEX_SIZE 9
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#define RADIX_PGD_INDEX_SIZE 13
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#endif /* _ASM_POWERPC_PGTABLE_RADIX_4K_H */
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@ -0,0 +1,12 @@
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#ifndef _ASM_POWERPC_PGTABLE_RADIX_64K_H
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#define _ASM_POWERPC_PGTABLE_RADIX_64K_H
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/*
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* For 64K page size supported index is 13/9/9/5
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*/
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#define RADIX_PTE_INDEX_SIZE 5 /* 2MB huge page */
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#define RADIX_PMD_INDEX_SIZE 9 /* 1G huge page */
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#define RADIX_PUD_INDEX_SIZE 9
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#define RADIX_PGD_INDEX_SIZE 13
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#endif /* _ASM_POWERPC_PGTABLE_RADIX_64K_H */
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@ -0,0 +1,125 @@
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#ifndef _ASM_POWERPC_PGTABLE_RADIX_H
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#define _ASM_POWERPC_PGTABLE_RADIX_H
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#ifndef __ASSEMBLY__
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#include <asm/cmpxchg.h>
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#endif
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#ifdef CONFIG_PPC_64K_PAGES
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#include <asm/book3s/64/radix-64k.h>
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#else
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#include <asm/book3s/64/radix-4k.h>
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#endif
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/* An empty PTE can still have a R or C writeback */
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#define RADIX_PTE_NONE_MASK (_PAGE_DIRTY | _PAGE_ACCESSED)
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/* Bits to set in a RPMD/RPUD/RPGD */
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#define RADIX_PMD_VAL_BITS (0x8000000000000000UL | RADIX_PTE_INDEX_SIZE)
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#define RADIX_PUD_VAL_BITS (0x8000000000000000UL | RADIX_PMD_INDEX_SIZE)
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#define RADIX_PGD_VAL_BITS (0x8000000000000000UL | RADIX_PUD_INDEX_SIZE)
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/* Don't have anything in the reserved bits and leaf bits */
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#define RADIX_PMD_BAD_BITS 0x60000000000000e0UL
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#define RADIX_PUD_BAD_BITS 0x60000000000000e0UL
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#define RADIX_PGD_BAD_BITS 0x60000000000000e0UL
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/*
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* Size of EA range mapped by our pagetables.
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*/
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#define RADIX_PGTABLE_EADDR_SIZE (RADIX_PTE_INDEX_SIZE + RADIX_PMD_INDEX_SIZE + \
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RADIX_PUD_INDEX_SIZE + RADIX_PGD_INDEX_SIZE + PAGE_SHIFT)
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#define RADIX_PGTABLE_RANGE (ASM_CONST(1) << RADIX_PGTABLE_EADDR_SIZE)
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#ifndef __ASSEMBLY__
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#define RADIX_PTE_TABLE_SIZE (sizeof(pte_t) << RADIX_PTE_INDEX_SIZE)
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#define RADIX_PMD_TABLE_SIZE (sizeof(pmd_t) << RADIX_PMD_INDEX_SIZE)
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#define RADIX_PUD_TABLE_SIZE (sizeof(pud_t) << RADIX_PUD_INDEX_SIZE)
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#define RADIX_PGD_TABLE_SIZE (sizeof(pgd_t) << RADIX_PGD_INDEX_SIZE)
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static inline unsigned long radix__pte_update(struct mm_struct *mm,
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unsigned long addr,
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pte_t *ptep, unsigned long clr,
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unsigned long set,
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int huge)
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{
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pte_t pte;
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unsigned long old_pte, new_pte;
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do {
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pte = READ_ONCE(*ptep);
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old_pte = pte_val(pte);
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new_pte = (old_pte | set) & ~clr;
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} while (!pte_xchg(ptep, __pte(old_pte), __pte(new_pte)));
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/* We already do a sync in cmpxchg, is ptesync needed ?*/
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asm volatile("ptesync" : : : "memory");
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/* huge pages use the old page table lock */
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if (!huge)
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assert_pte_locked(mm, addr);
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return old_pte;
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}
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/*
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* Set the dirty and/or accessed bits atomically in a linux PTE, this
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* function doesn't need to invalidate tlb.
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*/
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static inline void radix__ptep_set_access_flags(pte_t *ptep, pte_t entry)
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{
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pte_t pte;
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unsigned long old_pte, new_pte;
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unsigned long set = pte_val(entry) & (_PAGE_DIRTY | _PAGE_ACCESSED |
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_PAGE_RW | _PAGE_EXEC);
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do {
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pte = READ_ONCE(*ptep);
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old_pte = pte_val(pte);
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new_pte = old_pte | set;
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} while (!pte_xchg(ptep, __pte(old_pte), __pte(new_pte)));
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/* We already do a sync in cmpxchg, is ptesync needed ?*/
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asm volatile("ptesync" : : : "memory");
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}
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static inline int radix__pte_same(pte_t pte_a, pte_t pte_b)
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{
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return ((pte_raw(pte_a) ^ pte_raw(pte_b)) == 0);
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}
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static inline int radix__pte_none(pte_t pte)
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{
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return (pte_val(pte) & ~RADIX_PTE_NONE_MASK) == 0;
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}
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static inline void radix__set_pte_at(struct mm_struct *mm, unsigned long addr,
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pte_t *ptep, pte_t pte, int percpu)
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{
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*ptep = pte;
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asm volatile("ptesync" : : : "memory");
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}
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static inline int radix__pmd_bad(pmd_t pmd)
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{
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return !!(pmd_val(pmd) & RADIX_PMD_BAD_BITS);
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}
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static inline int radix__pmd_same(pmd_t pmd_a, pmd_t pmd_b)
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{
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return ((pmd_raw(pmd_a) ^ pmd_raw(pmd_b)) == 0);
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}
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static inline int radix__pud_bad(pud_t pud)
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{
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return !!(pud_val(pud) & RADIX_PUD_BAD_BITS);
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}
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static inline int radix__pgd_bad(pgd_t pgd)
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{
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return !!(pgd_val(pgd) & RADIX_PGD_BAD_BITS);
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}
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#endif /* __ASSEMBLY__ */
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#endif
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