ARM: net: bpf: improve 64-bit ALU implementation
Improbe the 64-bit ALU implementation from: movw r8, #65532 movt r8, #65535 movw r9, #65535 movt r9, #65535 ldr r7, [fp, #-44] adds r7, r7, r8 str r7, [fp, #-44] ldr r7, [fp, #-40] adc r7, r7, r9 str r7, [fp, #-40] to: movw r8, #65532 movt r8, #65535 movw r9, #65535 movt r9, #65535 ldrd r6, [fp, #-44] adds r6, r6, r8 adc r7, r7, r9 strd r6, [fp, #-44] Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
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@ -716,11 +716,30 @@ static inline void emit_a32_alu_r(const s8 dst, const s8 src,
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static inline void emit_a32_alu_r64(const bool is64, const s8 dst[],
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const s8 src[], struct jit_ctx *ctx,
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const u8 op) {
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emit_a32_alu_r(dst_lo, src_lo, ctx, is64, false, op);
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if (is64)
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emit_a32_alu_r(dst_hi, src_hi, ctx, is64, true, op);
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else
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emit_a32_mov_i(dst_hi, 0, ctx);
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const s8 *tmp = bpf2a32[TMP_REG_1];
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const s8 *tmp2 = bpf2a32[TMP_REG_2];
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const s8 *rd;
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rd = arm_bpf_get_reg64(dst, tmp, ctx);
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if (is64) {
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const s8 *rs;
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rs = arm_bpf_get_reg64(src, tmp2, ctx);
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/* ALU operation */
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emit_alu_r(rd[1], rs[1], true, false, op, ctx);
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emit_alu_r(rd[0], rs[0], true, true, op, ctx);
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} else {
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s8 rs;
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rs = arm_bpf_get_reg32(src_lo, tmp2[1], ctx);
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/* ALU operation */
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emit_alu_r(rd[1], rs, true, false, op, ctx);
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emit_a32_mov_i(rd[0], 0, ctx);
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}
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arm_bpf_put_reg64(dst, rd, ctx);
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}
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/* dst = src (4 bytes)*/
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