ARM: Spectre-BHB workaround
Workaround the Spectre BHB issues for Cortex-A15, Cortex-A57, Cortex-A72, Cortex-A73 and Cortex-A75. We also include Brahma B15 as well to be safe, which is affected by Spectre V2 in the same ways as Cortex-A15. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
This commit is contained in:
Russell King (Oracle)
parent
8d9d651ff2
commit
b9baf5c8c5
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@ -107,6 +107,16 @@
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.endm
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#endif
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#if __LINUX_ARM_ARCH__ < 7
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.macro dsb, args
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mcr p15, 0, r0, c7, c10, 4
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.endm
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.macro isb, args
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mcr p15, 0, r0, c7, r5, 4
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.endm
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#endif
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.macro asm_trace_hardirqs_off, save=1
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#if defined(CONFIG_TRACE_IRQFLAGS)
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.if \save
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@ -14,6 +14,7 @@ enum {
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__SPECTRE_V2_METHOD_ICIALLU,
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__SPECTRE_V2_METHOD_SMC,
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__SPECTRE_V2_METHOD_HVC,
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__SPECTRE_V2_METHOD_LOOP8,
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};
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enum {
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@ -21,8 +22,11 @@ enum {
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SPECTRE_V2_METHOD_ICIALLU = BIT(__SPECTRE_V2_METHOD_ICIALLU),
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SPECTRE_V2_METHOD_SMC = BIT(__SPECTRE_V2_METHOD_SMC),
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SPECTRE_V2_METHOD_HVC = BIT(__SPECTRE_V2_METHOD_HVC),
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SPECTRE_V2_METHOD_LOOP8 = BIT(__SPECTRE_V2_METHOD_LOOP8),
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};
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void spectre_v2_update_state(unsigned int state, unsigned int methods);
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int spectre_bhb_update_vectors(unsigned int method);
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#endif
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@ -116,11 +116,23 @@
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*/
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#define ARM_VECTORS \
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__vectors_lma = .; \
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.vectors 0xffff0000 : AT(__vectors_start) { \
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*(.vectors) \
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OVERLAY 0xffff0000 : NOCROSSREFS AT(__vectors_lma) { \
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.vectors { \
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*(.vectors) \
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} \
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.vectors.bhb.loop8 { \
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*(.vectors.bhb.loop8) \
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} \
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.vectors.bhb.bpiall { \
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*(.vectors.bhb.bpiall) \
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} \
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} \
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ARM_LMA(__vectors, .vectors); \
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. = __vectors_lma + SIZEOF(.vectors); \
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ARM_LMA(__vectors_bhb_loop8, .vectors.bhb.loop8); \
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ARM_LMA(__vectors_bhb_bpiall, .vectors.bhb.bpiall); \
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. = __vectors_lma + SIZEOF(.vectors) + \
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SIZEOF(.vectors.bhb.loop8) + \
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SIZEOF(.vectors.bhb.bpiall); \
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\
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__stubs_lma = .; \
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.stubs ADDR(.vectors) + 0x1000 : AT(__stubs_lma) { \
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@ -1002,12 +1002,11 @@ vector_\name:
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sub lr, lr, #\correction
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.endif
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@
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@ Save r0, lr_<exception> (parent PC) and spsr_<exception>
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@ (parent CPSR)
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@
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@ Save r0, lr_<exception> (parent PC)
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stmia sp, {r0, lr} @ save r0, lr
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mrs lr, spsr
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@ Save spsr_<exception> (parent CPSR)
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2: mrs lr, spsr
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str lr, [sp, #8] @ save spsr
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@
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@ -1028,6 +1027,44 @@ vector_\name:
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movs pc, lr @ branch to handler in SVC mode
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ENDPROC(vector_\name)
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#ifdef CONFIG_HARDEN_BRANCH_HISTORY
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.subsection 1
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.align 5
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vector_bhb_loop8_\name:
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.if \correction
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sub lr, lr, #\correction
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.endif
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@ Save r0, lr_<exception> (parent PC)
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stmia sp, {r0, lr}
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@ bhb workaround
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mov r0, #8
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1: b . + 4
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subs r0, r0, #1
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bne 1b
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dsb
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isb
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b 2b
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ENDPROC(vector_bhb_loop8_\name)
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vector_bhb_bpiall_\name:
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.if \correction
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sub lr, lr, #\correction
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.endif
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@ Save r0, lr_<exception> (parent PC)
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stmia sp, {r0, lr}
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@ bhb workaround
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mcr p15, 0, r0, c7, c5, 6 @ BPIALL
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@ isb not needed due to "movs pc, lr" in the vector stub
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@ which gives a "context synchronisation".
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b 2b
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ENDPROC(vector_bhb_bpiall_\name)
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.previous
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#endif
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.align 2
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@ handler addresses follow this label
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1:
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@ -1036,6 +1073,10 @@ ENDPROC(vector_\name)
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.section .stubs, "ax", %progbits
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@ This must be the first word
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.word vector_swi
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#ifdef CONFIG_HARDEN_BRANCH_HISTORY
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.word vector_bhb_loop8_swi
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.word vector_bhb_bpiall_swi
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#endif
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vector_rst:
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ARM( swi SYS_ERROR0 )
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@ -1150,8 +1191,10 @@ vector_addrexcptn:
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* FIQ "NMI" handler
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*-----------------------------------------------------------------------------
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* Handle a FIQ using the SVC stack allowing FIQ act like NMI on x86
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* systems.
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* systems. This must be the last vector stub, so lets place it in its own
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* subsection.
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*/
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.subsection 2
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vector_stub fiq, FIQ_MODE, 4
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.long __fiq_usr @ 0 (USR_26 / USR_32)
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@ -1184,6 +1227,30 @@ vector_addrexcptn:
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W(b) vector_irq
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W(b) vector_fiq
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#ifdef CONFIG_HARDEN_BRANCH_HISTORY
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.section .vectors.bhb.loop8, "ax", %progbits
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.L__vectors_bhb_loop8_start:
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W(b) vector_rst
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W(b) vector_bhb_loop8_und
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W(ldr) pc, .L__vectors_bhb_loop8_start + 0x1004
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W(b) vector_bhb_loop8_pabt
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W(b) vector_bhb_loop8_dabt
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W(b) vector_addrexcptn
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W(b) vector_bhb_loop8_irq
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W(b) vector_bhb_loop8_fiq
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.section .vectors.bhb.bpiall, "ax", %progbits
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.L__vectors_bhb_bpiall_start:
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W(b) vector_rst
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W(b) vector_bhb_bpiall_und
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W(ldr) pc, .L__vectors_bhb_bpiall_start + 0x1008
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W(b) vector_bhb_bpiall_pabt
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W(b) vector_bhb_bpiall_dabt
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W(b) vector_addrexcptn
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W(b) vector_bhb_bpiall_irq
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W(b) vector_bhb_bpiall_fiq
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#endif
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.data
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.align 2
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@ -153,6 +153,29 @@ ENDPROC(ret_from_fork)
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*-----------------------------------------------------------------------------
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*/
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.align 5
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#ifdef CONFIG_HARDEN_BRANCH_HISTORY
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ENTRY(vector_bhb_loop8_swi)
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sub sp, sp, #PT_REGS_SIZE
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stmia sp, {r0 - r12}
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mov r8, #8
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1: b 2f
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2: subs r8, r8, #1
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bne 1b
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dsb
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isb
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b 3f
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ENDPROC(vector_bhb_loop8_swi)
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.align 5
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ENTRY(vector_bhb_bpiall_swi)
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sub sp, sp, #PT_REGS_SIZE
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stmia sp, {r0 - r12}
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mcr p15, 0, r8, c7, c5, 6 @ BPIALL
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isb
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b 3f
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ENDPROC(vector_bhb_bpiall_swi)
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#endif
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.align 5
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ENTRY(vector_swi)
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#ifdef CONFIG_CPU_V7M
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@ -160,6 +183,7 @@ ENTRY(vector_swi)
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#else
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sub sp, sp, #PT_REGS_SIZE
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stmia sp, {r0 - r12} @ Calling r0 - r12
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3:
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ARM( add r8, sp, #S_PC )
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ARM( stmdb r8, {sp, lr}^ ) @ Calling sp, lr
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THUMB( mov r8, sp )
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@ -45,6 +45,10 @@ ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr,
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method = "Firmware call";
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break;
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case SPECTRE_V2_METHOD_LOOP8:
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method = "History overwrite";
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break;
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default:
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method = "Multiple mitigations";
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break;
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@ -30,6 +30,7 @@
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#include <linux/atomic.h>
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#include <asm/cacheflush.h>
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#include <asm/exception.h>
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#include <asm/spectre.h>
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#include <asm/unistd.h>
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#include <asm/traps.h>
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#include <asm/ptrace.h>
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@ -801,6 +802,43 @@ static void flush_vectors(void *vma, size_t offset, size_t size)
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flush_icache_range(start, end);
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}
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#ifdef CONFIG_HARDEN_BRANCH_HISTORY
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int spectre_bhb_update_vectors(unsigned int method)
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{
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extern char __vectors_bhb_bpiall_start[], __vectors_bhb_bpiall_end[];
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extern char __vectors_bhb_loop8_start[], __vectors_bhb_loop8_end[];
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void *vec_start, *vec_end;
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if (system_state >= SYSTEM_FREEING_INITMEM) {
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pr_err("CPU%u: Spectre BHB workaround too late - system vulnerable\n",
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smp_processor_id());
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return SPECTRE_VULNERABLE;
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}
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switch (method) {
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case SPECTRE_V2_METHOD_LOOP8:
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vec_start = __vectors_bhb_loop8_start;
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vec_end = __vectors_bhb_loop8_end;
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break;
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case SPECTRE_V2_METHOD_BPIALL:
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vec_start = __vectors_bhb_bpiall_start;
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vec_end = __vectors_bhb_bpiall_end;
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break;
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default:
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pr_err("CPU%u: unknown Spectre BHB state %d\n",
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smp_processor_id(), method);
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return SPECTRE_VULNERABLE;
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}
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copy_from_lma(vectors_page, vec_start, vec_end);
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flush_vectors(vectors_page, 0, vec_end - vec_start);
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return SPECTRE_MITIGATED;
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}
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#endif
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void __init early_trap_init(void *vectors_base)
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{
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extern char __stubs_start[], __stubs_end[];
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@ -851,6 +851,16 @@ config HARDEN_BRANCH_PREDICTOR
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If unsure, say Y.
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config HARDEN_BRANCH_HISTORY
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bool "Harden Spectre style attacks against branch history" if EXPERT
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depends on CPU_SPECTRE
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default y
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help
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Speculation attacks against some high-performance processors can
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make use of branch history to influence future speculation. When
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taking an exception, a sequence of branches overwrites the branch
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history, or branch history is invalidated.
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config TLS_REG_EMUL
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bool
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select NEED_KUSER_HELPERS
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@ -177,6 +177,81 @@ static void cpu_v7_spectre_v2_init(void)
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spectre_v2_update_state(state, method);
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}
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#ifdef CONFIG_HARDEN_BRANCH_HISTORY
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static int spectre_bhb_method;
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static const char *spectre_bhb_method_name(int method)
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{
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switch (method) {
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case SPECTRE_V2_METHOD_LOOP8:
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return "loop";
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case SPECTRE_V2_METHOD_BPIALL:
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return "BPIALL";
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default:
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return "unknown";
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}
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}
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static int spectre_bhb_install_workaround(int method)
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{
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if (spectre_bhb_method != method) {
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if (spectre_bhb_method) {
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pr_err("CPU%u: Spectre BHB: method disagreement, system vulnerable\n",
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smp_processor_id());
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return SPECTRE_VULNERABLE;
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}
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if (spectre_bhb_update_vectors(method) == SPECTRE_VULNERABLE)
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return SPECTRE_VULNERABLE;
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spectre_bhb_method = method;
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}
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pr_info("CPU%u: Spectre BHB: using %s workaround\n",
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smp_processor_id(), spectre_bhb_method_name(method));
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return SPECTRE_MITIGATED;
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}
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#else
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static int spectre_bhb_install_workaround(int method)
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{
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return SPECTRE_VULNERABLE;
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}
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#endif
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static void cpu_v7_spectre_bhb_init(void)
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{
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unsigned int state, method = 0;
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switch (read_cpuid_part()) {
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case ARM_CPU_PART_CORTEX_A15:
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case ARM_CPU_PART_BRAHMA_B15:
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case ARM_CPU_PART_CORTEX_A57:
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case ARM_CPU_PART_CORTEX_A72:
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state = SPECTRE_MITIGATED;
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method = SPECTRE_V2_METHOD_LOOP8;
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break;
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case ARM_CPU_PART_CORTEX_A73:
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case ARM_CPU_PART_CORTEX_A75:
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state = SPECTRE_MITIGATED;
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method = SPECTRE_V2_METHOD_BPIALL;
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break;
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default:
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state = SPECTRE_UNAFFECTED;
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break;
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}
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if (state == SPECTRE_MITIGATED)
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state = spectre_bhb_install_workaround(method);
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spectre_v2_update_state(state, method);
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}
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static __maybe_unused bool cpu_v7_check_auxcr_set(bool *warned,
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u32 mask, const char *msg)
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{
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@ -217,4 +292,5 @@ void cpu_v7_ca15_ibe(void)
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void cpu_v7_bugs_init(void)
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{
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cpu_v7_spectre_v2_init();
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cpu_v7_spectre_bhb_init();
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}
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