irqchip/meson-gpio: Add support for meson s4 SoCs
The meson s4 SoCs support 12 gpio irq lines compared with previous serial chips and have something different, details are as below. IRQ Number: - 80:68 13 pins on bank Z - 67:48 20 pins on bank X - 47:36 12 pins on bank H - 35:24 12 pins on bank D - 23:22 2 pins on bank E - 21:14 8 pins on bank C - 13:0 13 pins on bank B Signed-off-by: Qianggui Song <qianggui.song@amlogic.com> [maz: fixed some W=1 build warnings] Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220225055207.1048-5-qianggui.song@amlogic.com
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@ -26,6 +26,8 @@
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/* use for A1 like chips */
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/* use for A1 like chips */
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#define REG_PIN_A1_SEL 0x04
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#define REG_PIN_A1_SEL 0x04
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/* Used for s4 chips */
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#define REG_EDGE_POL_S4 0x1c
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/*
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/*
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* Note: The S905X3 datasheet reports that BOTH_EDGE is controlled by
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* Note: The S905X3 datasheet reports that BOTH_EDGE is controlled by
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@ -53,6 +55,8 @@ static void meson_a1_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl,
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static void meson_a1_gpio_irq_init(struct meson_gpio_irq_controller *ctl);
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static void meson_a1_gpio_irq_init(struct meson_gpio_irq_controller *ctl);
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static int meson8_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl,
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static int meson8_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl,
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unsigned int type, u32 *channel_hwirq);
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unsigned int type, u32 *channel_hwirq);
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static int meson_s4_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl,
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unsigned int type, u32 *channel_hwirq);
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struct irq_ctl_ops {
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struct irq_ctl_ops {
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void (*gpio_irq_sel_pin)(struct meson_gpio_irq_controller *ctl,
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void (*gpio_irq_sel_pin)(struct meson_gpio_irq_controller *ctl,
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@ -101,6 +105,17 @@ struct meson_gpio_irq_params {
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.pin_sel_mask = 0x7f, \
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.pin_sel_mask = 0x7f, \
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.nr_channels = 8, \
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.nr_channels = 8, \
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#define INIT_MESON_S4_COMMON_DATA(irqs) \
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INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init, \
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meson_a1_gpio_irq_sel_pin, \
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meson_s4_gpio_irq_set_type) \
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.support_edge_both = true, \
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.edge_both_offset = 0, \
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.edge_single_offset = 12, \
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.pol_low_offset = 0, \
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.pin_sel_mask = 0xff, \
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.nr_channels = 12, \
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static const struct meson_gpio_irq_params meson8_params = {
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static const struct meson_gpio_irq_params meson8_params = {
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INIT_MESON8_COMMON_DATA(134)
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INIT_MESON8_COMMON_DATA(134)
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};
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};
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@ -131,6 +146,10 @@ static const struct meson_gpio_irq_params a1_params = {
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INIT_MESON_A1_COMMON_DATA(62)
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INIT_MESON_A1_COMMON_DATA(62)
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};
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};
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static const struct meson_gpio_irq_params s4_params = {
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INIT_MESON_S4_COMMON_DATA(82)
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};
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static const struct of_device_id meson_irq_gpio_matches[] = {
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static const struct of_device_id meson_irq_gpio_matches[] = {
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{ .compatible = "amlogic,meson8-gpio-intc", .data = &meson8_params },
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{ .compatible = "amlogic,meson8-gpio-intc", .data = &meson8_params },
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{ .compatible = "amlogic,meson8b-gpio-intc", .data = &meson8b_params },
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{ .compatible = "amlogic,meson8b-gpio-intc", .data = &meson8b_params },
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@ -140,6 +159,7 @@ static const struct of_device_id meson_irq_gpio_matches[] = {
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{ .compatible = "amlogic,meson-g12a-gpio-intc", .data = &axg_params },
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{ .compatible = "amlogic,meson-g12a-gpio-intc", .data = &axg_params },
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{ .compatible = "amlogic,meson-sm1-gpio-intc", .data = &sm1_params },
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{ .compatible = "amlogic,meson-sm1-gpio-intc", .data = &sm1_params },
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{ .compatible = "amlogic,meson-a1-gpio-intc", .data = &a1_params },
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{ .compatible = "amlogic,meson-a1-gpio-intc", .data = &a1_params },
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{ .compatible = "amlogic,meson-s4-gpio-intc", .data = &s4_params },
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{ }
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{ }
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};
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};
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@ -308,6 +328,51 @@ static int meson8_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl,
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return 0;
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return 0;
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}
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}
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/*
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* gpio irq relative registers for s4
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* -PADCTRL_GPIO_IRQ_CTRL0
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* bit[31]: enable/disable all the irq lines
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* bit[12-23]: single edge trigger
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* bit[0-11]: polarity trigger
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*
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* -PADCTRL_GPIO_IRQ_CTRL[X]
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* bit[0-16]: 7 bits to choose gpio source for irq line 2*[X] - 2
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* bit[16-22]:7 bits to choose gpio source for irq line 2*[X] - 1
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* where X = 1-6
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*
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* -PADCTRL_GPIO_IRQ_CTRL[7]
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* bit[0-11]: both edge trigger
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*/
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static int meson_s4_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl,
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unsigned int type, u32 *channel_hwirq)
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{
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u32 val = 0;
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unsigned int idx;
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idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq);
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type &= IRQ_TYPE_SENSE_MASK;
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meson_gpio_irq_update_bits(ctl, REG_EDGE_POL_S4, BIT(idx), 0);
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if (type == IRQ_TYPE_EDGE_BOTH) {
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val |= BIT(ctl->params->edge_both_offset + idx);
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meson_gpio_irq_update_bits(ctl, REG_EDGE_POL_S4,
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BIT(ctl->params->edge_both_offset + idx), val);
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return 0;
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}
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if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))
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val |= BIT(ctl->params->pol_low_offset + idx);
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if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
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val |= BIT(ctl->params->edge_single_offset + idx);
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meson_gpio_irq_update_bits(ctl, REG_EDGE_POL,
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BIT(idx) | BIT(12 + idx), val);
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return 0;
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};
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static unsigned int meson_gpio_irq_type_output(unsigned int type)
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static unsigned int meson_gpio_irq_type_output(unsigned int type)
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{
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{
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unsigned int sense = type & IRQ_TYPE_SENSE_MASK;
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unsigned int sense = type & IRQ_TYPE_SENSE_MASK;
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