watchdog: rzg2l_wdt: Add rzv2m support
The WDT on RZ/V2M devices is basically the same as RZ/G2L, but without the parity error registers. This means the driver has to reset the hardware plus set the minimum timeout in order to do a restart and has a single interrupt. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Link: https://lore.kernel.org/r/20220823093233.8577-3-phil.edworthy@renesas.com Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
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parent
d59913b0a5
commit
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drivers/watchdog
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@ -10,7 +10,7 @@
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/reset.h>
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@ -40,6 +40,11 @@ module_param(nowayout, bool, 0);
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MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
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__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
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enum rz_wdt_type {
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WDT_RZG2L,
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WDT_RZV2M,
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};
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struct rzg2l_wdt_priv {
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void __iomem *base;
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struct watchdog_device wdev;
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@ -48,6 +53,7 @@ struct rzg2l_wdt_priv {
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unsigned long delay;
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struct clk *pclk;
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struct clk *osc_clk;
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enum rz_wdt_type devtype;
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};
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static void rzg2l_wdt_wait_delay(struct rzg2l_wdt_priv *priv)
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@ -142,11 +148,29 @@ static int rzg2l_wdt_restart(struct watchdog_device *wdev,
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clk_prepare_enable(priv->pclk);
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clk_prepare_enable(priv->osc_clk);
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/* Generate Reset (WDTRSTB) Signal on parity error */
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rzg2l_wdt_write(priv, 0, PECR);
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if (priv->devtype == WDT_RZG2L) {
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/* Generate Reset (WDTRSTB) Signal on parity error */
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rzg2l_wdt_write(priv, 0, PECR);
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/* Force parity error */
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rzg2l_wdt_write(priv, PEEN_FORCE, PEEN);
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/* Force parity error */
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rzg2l_wdt_write(priv, PEEN_FORCE, PEEN);
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} else {
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/* RZ/V2M doesn't have parity error registers */
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wdev->timeout = 0;
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/* Initialize time out */
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rzg2l_wdt_init_timeout(wdev);
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/* Initialize watchdog counter register */
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rzg2l_wdt_write(priv, 0, WDTTIM);
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/* Enable watchdog timer*/
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rzg2l_wdt_write(priv, WDTCNT_WDTEN, WDTCNT);
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/* Wait 2 consecutive overflow cycles for reset */
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mdelay(DIV_ROUND_UP(2 * 0xFFFFF * 1000, priv->osc_clk_rate));
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}
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return 0;
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}
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@ -227,6 +251,8 @@ static int rzg2l_wdt_probe(struct platform_device *pdev)
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if (ret)
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return dev_err_probe(dev, ret, "failed to deassert");
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priv->devtype = (uintptr_t)of_device_get_match_data(dev);
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pm_runtime_enable(&pdev->dev);
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priv->wdev.info = &rzg2l_wdt_ident;
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@ -255,7 +281,8 @@ static int rzg2l_wdt_probe(struct platform_device *pdev)
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}
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static const struct of_device_id rzg2l_wdt_ids[] = {
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{ .compatible = "renesas,rzg2l-wdt", },
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{ .compatible = "renesas,rzg2l-wdt", .data = (void *)WDT_RZG2L },
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{ .compatible = "renesas,rzv2m-wdt", .data = (void *)WDT_RZV2M },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, rzg2l_wdt_ids);
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