ARC: [plat-axs10x] DTS: Add reset controller node to manage ethernet reset
DW ethernet controller on axs10x hangs sometimes after SW reset. Invoke the newly aded driver (reset-axs10x.c) by adding the DT bits. With this in place, we don't need the open-coded quirk in platform code, so get rid of it as well ! Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
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@ -16,6 +16,12 @@
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ranges = <0x00000000 0x0 0xe0000000 0x10000000>;
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interrupt-parent = <&mb_intc>;
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creg_rst: reset-controller@11220 {
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compatible = "snps,axs10x-reset";
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#reset-cells = <1>;
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reg = <0x11220 0x4>;
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};
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i2sclk: i2sclk@100a0 {
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compatible = "snps,axs10x-i2s-pll-clock";
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reg = <0x100a0 0x10>;
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@ -73,6 +79,8 @@
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clocks = <&apbclk>;
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clock-names = "stmmaceth";
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max-speed = <100>;
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resets = <&creg_rst 5>;
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reset-names = "stmmaceth";
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};
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ehci@0x40000 {
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@ -111,13 +111,6 @@ static void __init axs10x_early_init(void)
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axs10x_enable_gpio_intc_wire();
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/*
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* Reset ethernet IP core.
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* TODO: get rid of this quirk after axs10x reset driver (or simple
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* reset driver) will be available in upstream.
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*/
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iowrite32((1 << 5), (void __iomem *) CREG_MB_SW_RESET);
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scnprintf(mb, 32, "MainBoard v%d", mb_rev);
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axs10x_print_board_ver(CREG_MB_VER, mb);
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}
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