On omap24xx, INTCPS_SIR_IRQ_OFFSET bits [6:0] contains the current
active interrupt number.
However, on 34xx INTCPS_SIR_IRQ_OFFSET bits [31:7] also contains the
SPURIOUSIRQFLAG, which gets set if the interrupt sorting information
is invalid.
If the SPURIOUSIRQFLAG bits are not ignored, the interrupt code will
occasionally produce a bunch of confusing errors:
irq -33, desc: c02ddcc8, depth: 0, count: 0, unhandled: 0
->handle_irq(): c006f23c, handle_bad_irq+0x0/0x22c
->chip(): 00000000, 0x0
->action(): 00000000
Fix this by masking out only the ACTIVEIRQ bits. Also fix a
confusing comment.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add minimal omap3430 support based on earlier patches from
Syed Mohammed Khasim. Also merge in omap34xx SRAM support
from Karthik Dasu and use consistent naming for sram init
functions.
Also do following changes that make 34xx support usable:
- Remove unused sram.c functions for 34xx
- Rename IRQ_SIR_IRQ to INTCPS_SIR_IRQ and define it locally
in entry-macro.S
- Update mach-omap2/io.c to support 2420, 2430, and 34xx
- Also merge in 34xx GPMC changes to add fields wr_access and
wr_data_mux_bus from Adrian Hunter
- Remove memory initialization call omap2_init_memory() until
until more generic memory initialization patches are posted.
It's OK to rely on bootloader initialization until then.
Signed-off-by: Syed Mohammed, Khasim <khasim@ti.com>
Signed-off-by: Karthik Dasu<karthik-dp@ti.com>
Signed-off-by: Adrian Hunter <ext-adrian.hunter@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Tony Lindgren
Syed Mohammed, Khasim
Russell King