Commit Graph

8 Commits

Author SHA1 Message Date
Sekhar Nori 48519f0ae0 ASoC: davinci: let platform data define edma queue numbers
Currently the EDMA queue to be used by for servicing ASP through
internal RAM is fixed to EDMAQ_0 and that to service internal RAM
from external RAM is fixed to EDMAQ_1.

This may not be the desirable configuration on all platforms. For
example, on DM365, queue 0 has large fifo size and is more suitable
for video transfers. Having audio and video transfers on the same
queue may lead to starvation on audio side.

platform data as defined currently passes a queue number to the driver
but that remains unused inside the driver.

Fix this by defining one queue each for ASP and RAM transfers in the
platform data and using it inside the driver.

Since EDMAQ_0 maps to 0, thats the queue that will be used if
the asp queue number is not initialized. None of the platforms
currently utilize ping-pong transfers through internal RAM so that
functionality remains unchanged too.

This patch has been tested on DM644x and OMAP-L138 EVMs.

Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2010-07-20 09:57:20 +01:00
Troy Kisky 1e224f322b ASoC: DaVinci: pcm, fix underrun by using sram
Fix underruns by using dma to copy 1st to sram
in a ping/pong buffer style and then copying from
the sram to the ASP. This also has the advantage
of tolerating very long interrupt latency on dma
completion.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2009-11-19 10:48:08 +00:00
Chaithrika U S 4fa9c1a595 ASoC: DaVinci: McASP FIFO related updates
The DMA params for McASP with FIFO has been updated so that it works for
various FIFO levels. A member- 'fifo_level' has been added to the DMA
params data structure. The fifo_level can be adjusted by the tx[rx]_numevt
platform data. This is relevant only for DA8xx/OMAP-L1xx platforms. This
implementation has been tested for numevt values 1, 2, 4, 8.

Signed-off-by: Chaithrika U S <chaithrika@ti.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2009-09-30 13:43:55 +01:00
Troy Kisky 92e2a6f682 ASoC: Davinci: Fix race with cpu_dai->dma_data
This patch removes references to cpu_dai->dma_data.
It makes struct davinci_pcm_dma_params part of
struct davinci_mcbsp_dev or struct davinci_audio_dev.

It removes the unused name variable from davinci_pcm_dma_params.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2009-09-23 10:08:57 -07:00
Chaithrika U S 6a99fb5fb8 ASoC: DaVinci: McASP driver enhacements
On DA830/OMAP-L137 and DA850/OMAP-L138 SoCs, the McASP peripheral has FIFO
support. This FIFO provides additional data buffering. It also provides
tolerance to variation in host/DMA controller response times.
The read and write FIFO sizes are 256 bytes each. If FIFO is enabled,
the DMA events from McASP are sent to the FIFO which in turn sends DMA requests
to the host CPU according to the thresholds programmed.
More details of the FIFO operation can be found at
http://focus.ti.com/general/docs/lit/getliterature.tsp?literatureNumber=
sprufm1&fileType=pdf

This patch adds support for FIFO configuration. The platform data has a
version field which differentiates the McASP on different SoCs.

Signed-off-by: Chaithrika U S <chaithrika@ti.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2009-08-13 22:19:35 +01:00
Chaithrika U S b67f448729 ASoC: Add mcasp support for DM646x
Adds driver support for the two instances of McASP on TI's DM646x.

The multichannel audio serial port (McASP) functions as a general-purpose audio
serial port optimized for the needs of multichannel audio application.
(http://www.ti.com/litv/pdf/spruer1b).

There are two instances of McASP on DM646x. The McASP0 module includes up to 4
serializers that can be individually enabled to either transmit or receive
in different modes. The McASP1 module is limited with only 1 pinned-out
serializer that can be enabled to only transmit in DIT mode (neither receiving
in any mode nor transmitting in either Burst or TDM mode is supported).

McASP0 consists of transmit and receive sections that may operate
synchronized, or completely independently with separate master clocks, bit
clocks, and frame syncs, and using different transmit modes with different
bit-stream formats.

Signed-off-by: Steve Chen <schen@mvista.com>
Signed-off-by: Pavel Kiryukhin <pkiryukhin@ru.mvista.com>
Signed-off-by: Naresh Medisetty <naresh@ti.com>
Signed-off-by: Chaithrika U S <chaithrika@ti.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2009-06-07 20:10:01 +01:00
Vladimir Barinov d6b52039c9 ALSA: Correct Vladimir Barinov's e-mail address
Signed-off-by: Takashi Iwai <tiwai@suse.de>
Signed-off-by: Jaroslav Kysela <perex@perex.cz>
2008-10-10 13:41:45 +02:00
Vladimir Barinov 310355c111 [ALSA] Davinci ASoC support
Add ASoC support for the TI Davinci SoC and the Davicni-EVM reference board.
It includes:
- ASoC Davinci DMA driver
- ASoC Davinci I2S (Davinci McBSP module based) driver
- ASoC Davinci-EVM reference board

Signed-off-by: Vladimir Barinov <vbarinov@ru.mvista.com>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
2008-04-24 12:00:11 +02:00