This commit enables several interfaces of the CP side of the Armada
7040 for the Armada 7040 DB board:
- one PCIe interface
- one SPI controller with an attached SPI flash
- one I2C controller
- one SATA controller
- two USB3 controllers
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
This commit slightly improves the description of the SPI flash
connected to the SPI controller of the Armada 7040, by:
- Using the more generic "jedec,spi-nor" compatible string, which
lets the driver auto-detect the exact SPI flash type.
- Removing the silly comment about the Chip Select, since reg = <0>
is explicit enough.
- Switching to the new Device Tree binding to describe flash
partitions.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
This commit adds the necessary UART aliases to the main Armada 7K/8K
.dtsi file, and uses them to define the /chosen/stdout-path property
on the Armada 7040 DB board.
Suggested-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Instead of duplicating the node hierarchy, reference the nodes by label,
adding labels where necessary.
Drop some trailing or inconsistent white lines while at it.
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
[Thomas: drop Fixes tag as it is not a bug fix.]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
This commit adds the base Device Tree files for the Armada 7K and 8K
SoCs, as well as the Armada 8040 DB board.
The Armada 7020, 7040 (7K family) and 8020, 8040 (8K family) are
composed of:
- An AP806 block that contains the CPU core and a few basic
peripherals. The AP806 is available in dual core configurations
(used in 7020 and 8020) and quad core configurations (used in 8020
and 8040).
- One or two CP110 blocks that contain all the high-speed interfaces
(SATA, PCIe, Ethernet, etc.). The 7K family chips have one CP110,
and the 8K family chips have two CP110, giving them twice the
number of HW interfaces.
In order to represent this from a Device Tree point of view, this
commit creates the following hierarchy:
* armada-ap806.dtsi - definitions common to dual/quad ap806
* armada-ap806-dual.dtsi - description of the two CPUs
* armada-7020.dtsi - description of the 7020 SoC
* armada-8020.dtsi - description of the 8020 SoC
* armada-ap806-quad.dtsi - description of the four CPUs
* armada-7040.dtsi - description of the 7040 SoC
* armada-7040-db.dts - description of the 7040 board
* armada-8040.dtsi - description of the 8040 SoC
The CP110 blocks are not described yet, and will be part of future
patch series.
[gregory.clement@free-electrons.com: Fix commit title by adding ' dts:']
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Thomas Petazzoni
Andreas Färber