134 lines
6.4 KiB
ReStructuredText
134 lines
6.4 KiB
ReStructuredText
.. SPDX-License-Identifier: GPL-2.0
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=====================
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AMD Memory Encryption
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=====================
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Secure Memory Encryption (SME) and Secure Encrypted Virtualization (SEV) are
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features found on AMD processors.
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SME provides the ability to mark individual pages of memory as encrypted using
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the standard x86 page tables. A page that is marked encrypted will be
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automatically decrypted when read from DRAM and encrypted when written to
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DRAM. SME can therefore be used to protect the contents of DRAM from physical
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attacks on the system.
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SEV enables running encrypted virtual machines (VMs) in which the code and data
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of the guest VM are secured so that a decrypted version is available only
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within the VM itself. SEV guest VMs have the concept of private and shared
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memory. Private memory is encrypted with the guest-specific key, while shared
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memory may be encrypted with hypervisor key. When SME is enabled, the hypervisor
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key is the same key which is used in SME.
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A page is encrypted when a page table entry has the encryption bit set (see
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below on how to determine its position). The encryption bit can also be
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specified in the cr3 register, allowing the PGD table to be encrypted. Each
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successive level of page tables can also be encrypted by setting the encryption
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bit in the page table entry that points to the next table. This allows the full
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page table hierarchy to be encrypted. Note, this means that just because the
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encryption bit is set in cr3, doesn't imply the full hierarchy is encrypted.
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Each page table entry in the hierarchy needs to have the encryption bit set to
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achieve that. So, theoretically, you could have the encryption bit set in cr3
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so that the PGD is encrypted, but not set the encryption bit in the PGD entry
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for a PUD which results in the PUD pointed to by that entry to not be
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encrypted.
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When SEV is enabled, instruction pages and guest page tables are always treated
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as private. All the DMA operations inside the guest must be performed on shared
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memory. Since the memory encryption bit is controlled by the guest OS when it
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is operating in 64-bit or 32-bit PAE mode, in all other modes the SEV hardware
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forces the memory encryption bit to 1.
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Support for SME and SEV can be determined through the CPUID instruction. The
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CPUID function 0x8000001f reports information related to SME::
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0x8000001f[eax]:
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Bit[0] indicates support for SME
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Bit[1] indicates support for SEV
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0x8000001f[ebx]:
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Bits[5:0] pagetable bit number used to activate memory
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encryption
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Bits[11:6] reduction in physical address space, in bits, when
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memory encryption is enabled (this only affects
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system physical addresses, not guest physical
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addresses)
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If support for SME is present, MSR 0xc00100010 (MSR_AMD64_SYSCFG) can be used to
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determine if SME is enabled and/or to enable memory encryption::
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0xc0010010:
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Bit[23] 0 = memory encryption features are disabled
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1 = memory encryption features are enabled
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If SEV is supported, MSR 0xc0010131 (MSR_AMD64_SEV) can be used to determine if
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SEV is active::
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0xc0010131:
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Bit[0] 0 = memory encryption is not active
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1 = memory encryption is active
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Linux relies on BIOS to set this bit if BIOS has determined that the reduction
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in the physical address space as a result of enabling memory encryption (see
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CPUID information above) will not conflict with the address space resource
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requirements for the system. If this bit is not set upon Linux startup then
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Linux itself will not set it and memory encryption will not be possible.
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The state of SME in the Linux kernel can be documented as follows:
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- Supported:
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The CPU supports SME (determined through CPUID instruction).
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- Enabled:
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Supported and bit 23 of MSR_AMD64_SYSCFG is set.
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- Active:
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Supported, Enabled and the Linux kernel is actively applying
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the encryption bit to page table entries (the SME mask in the
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kernel is non-zero).
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SME can also be enabled and activated in the BIOS. If SME is enabled and
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activated in the BIOS, then all memory accesses will be encrypted and it
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will not be necessary to activate the Linux memory encryption support.
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If the BIOS merely enables SME (sets bit 23 of the MSR_AMD64_SYSCFG),
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then memory encryption can be enabled by supplying mem_encrypt=on on the
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kernel command line. However, if BIOS does not enable SME, then Linux
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will not be able to activate memory encryption, even if configured to do
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so by default or the mem_encrypt=on command line parameter is specified.
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Secure Nested Paging (SNP)
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==========================
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SEV-SNP introduces new features (SEV_FEATURES[1:63]) which can be enabled
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by the hypervisor for security enhancements. Some of these features need
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guest side implementation to function correctly. The below table lists the
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expected guest behavior with various possible scenarios of guest/hypervisor
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SNP feature support.
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+-----------------+---------------+---------------+------------------+
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| Feature Enabled | Guest needs | Guest has | Guest boot |
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| by the HV | implementation| implementation| behaviour |
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+=================+===============+===============+==================+
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| No | No | No | Boot |
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| | | | |
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+-----------------+---------------+---------------+------------------+
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| No | Yes | No | Boot |
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| | | | |
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+-----------------+---------------+---------------+------------------+
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| No | Yes | Yes | Boot |
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+-----------------+---------------+---------------+------------------+
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| Yes | No | No | Boot with |
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| | | | feature enabled |
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+-----------------+---------------+---------------+------------------+
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| Yes | Yes | No | Graceful boot |
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| | | | failure |
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+-----------------+---------------+---------------+------------------+
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| Yes | Yes | Yes | Boot with |
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| | | | feature enabled |
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+-----------------+---------------+---------------+------------------+
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More details in AMD64 APM[1] Vol 2: 15.34.10 SEV_STATUS MSR
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[1] https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/24593.pdf
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