153 lines
3.2 KiB
ArmAsm
153 lines
3.2 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* linux/arch/arm/vfp/vfphw.S
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*
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* Copyright (C) 2004 ARM Limited.
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* Written by Deep Blue Solutions Limited.
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*/
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#include <linux/init.h>
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#include <linux/linkage.h>
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#include <asm/thread_info.h>
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#include <asm/vfpmacros.h>
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#include <linux/kern_levels.h>
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#include <asm/assembler.h>
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#include <asm/asm-offsets.h>
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.macro DBGSTR1, str, arg
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#ifdef DEBUG
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stmfd sp!, {r0-r3, ip, lr}
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mov r1, \arg
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ldr r0, =1f
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bl _printk
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ldmfd sp!, {r0-r3, ip, lr}
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.pushsection .rodata, "a"
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1: .ascii KERN_DEBUG "VFP: \str\n"
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.byte 0
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.previous
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#endif
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.endm
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ENTRY(vfp_load_state)
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@ Load the current VFP state
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@ r0 - load location
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@ returns FPEXC
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DBGSTR1 "load VFP state %p", r0
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@ Load the saved state back into the VFP
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VFPFLDMIA r0, r1 @ reload the working registers while
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@ FPEXC is in a safe state
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ldmia r0, {r0-r3} @ load FPEXC, FPSCR, FPINST, FPINST2
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tst r0, #FPEXC_EX @ is there additional state to restore?
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beq 1f
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VFPFMXR FPINST, r2 @ restore FPINST (only if FPEXC.EX is set)
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tst r0, #FPEXC_FP2V @ is there an FPINST2 to write?
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beq 1f
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VFPFMXR FPINST2, r3 @ FPINST2 if needed (and present)
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1:
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VFPFMXR FPSCR, r1 @ restore status
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ret lr
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ENDPROC(vfp_load_state)
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ENTRY(vfp_save_state)
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@ Save the current VFP state
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@ r0 - save location
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@ r1 - FPEXC
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DBGSTR1 "save VFP state %p", r0
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VFPFSTMIA r0, r2 @ save the working registers
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VFPFMRX r2, FPSCR @ current status
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tst r1, #FPEXC_EX @ is there additional state to save?
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beq 1f
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VFPFMRX r3, FPINST @ FPINST (only if FPEXC.EX is set)
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tst r1, #FPEXC_FP2V @ is there an FPINST2 to read?
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beq 1f
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VFPFMRX r12, FPINST2 @ FPINST2 if needed (and present)
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1:
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stmia r0, {r1, r2, r3, r12} @ save FPEXC, FPSCR, FPINST, FPINST2
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ret lr
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ENDPROC(vfp_save_state)
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.macro tbl_branch, base, tmp, shift
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#ifdef CONFIG_THUMB2_KERNEL
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adr \tmp, 1f
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add \tmp, \tmp, \base, lsl \shift
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ret \tmp
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#else
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add pc, pc, \base, lsl \shift
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mov r0, r0
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#endif
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1:
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.endm
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ENTRY(vfp_get_float)
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tbl_branch r0, r3, #3
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.fpu vfpv2
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.irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
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1: vmov r0, s\dr
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ret lr
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.org 1b + 8
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.endr
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.irp dr,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
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1: vmov r0, s\dr
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ret lr
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.org 1b + 8
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.endr
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ENDPROC(vfp_get_float)
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ENTRY(vfp_put_float)
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tbl_branch r1, r3, #3
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.fpu vfpv2
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.irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
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1: vmov s\dr, r0
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ret lr
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.org 1b + 8
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.endr
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.irp dr,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
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1: vmov s\dr, r0
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ret lr
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.org 1b + 8
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.endr
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ENDPROC(vfp_put_float)
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ENTRY(vfp_get_double)
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tbl_branch r0, r3, #3
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.fpu vfpv2
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.irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
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1: vmov r0, r1, d\dr
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ret lr
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.org 1b + 8
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.endr
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#ifdef CONFIG_VFPv3
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@ d16 - d31 registers
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.fpu vfpv3
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.irp dr,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
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1: vmov r0, r1, d\dr
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ret lr
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.org 1b + 8
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.endr
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#endif
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@ virtual register 16 (or 32 if VFPv3) for compare with zero
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mov r0, #0
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mov r1, #0
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ret lr
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ENDPROC(vfp_get_double)
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ENTRY(vfp_put_double)
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tbl_branch r2, r3, #3
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.fpu vfpv2
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.irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
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1: vmov d\dr, r0, r1
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ret lr
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.org 1b + 8
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.endr
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#ifdef CONFIG_VFPv3
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.fpu vfpv3
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@ d16 - d31 registers
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.irp dr,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
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1: vmov d\dr, r0, r1
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ret lr
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.org 1b + 8
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.endr
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#endif
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ENDPROC(vfp_put_double)
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