117 lines
3.6 KiB
C
117 lines
3.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2012 ARM Ltd.
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*/
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#ifndef __ASM_MMU_H
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#define __ASM_MMU_H
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#include <asm/cputype.h>
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#define MMCF_AARCH32 0x1 /* mm context flag for AArch32 executables */
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#define USER_ASID_BIT 48
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#define USER_ASID_FLAG (UL(1) << USER_ASID_BIT)
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#define TTBR_ASID_MASK (UL(0xffff) << 48)
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#ifndef __ASSEMBLY__
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#include <linux/refcount.h>
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#include <asm/cpufeature.h>
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typedef struct {
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atomic64_t id;
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#ifdef CONFIG_COMPAT
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void *sigpage;
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#endif
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refcount_t pinned;
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void *vdso;
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unsigned long flags;
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} mm_context_t;
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/*
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* We use atomic64_read() here because the ASID for an 'mm_struct' can
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* be reallocated when scheduling one of its threads following a
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* rollover event (see new_context() and flush_context()). In this case,
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* a concurrent TLBI (e.g. via try_to_unmap_one() and ptep_clear_flush())
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* may use a stale ASID. This is fine in principle as the new ASID is
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* guaranteed to be clean in the TLB, but the TLBI routines have to take
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* care to handle the following race:
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*
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* CPU 0 CPU 1 CPU 2
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*
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* // ptep_clear_flush(mm)
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* xchg_relaxed(pte, 0)
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* DSB ISHST
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* old = ASID(mm)
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* | <rollover>
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* | new = new_context(mm)
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* \-----------------> atomic_set(mm->context.id, new)
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* cpu_switch_mm(mm)
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* // Hardware walk of pte using new ASID
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* TLBI(old)
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*
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* In this scenario, the barrier on CPU 0 and the dependency on CPU 1
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* ensure that the page-table walker on CPU 1 *must* see the invalid PTE
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* written by CPU 0.
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*/
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#define ASID(mm) (atomic64_read(&(mm)->context.id) & 0xffff)
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static inline bool arm64_kernel_unmapped_at_el0(void)
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{
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return alternative_has_cap_unlikely(ARM64_UNMAP_KERNEL_AT_EL0);
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}
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extern void arm64_memblock_init(void);
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extern void paging_init(void);
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extern void bootmem_init(void);
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extern void __iomem *early_io_map(phys_addr_t phys, unsigned long virt);
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extern void create_mapping_noalloc(phys_addr_t phys, unsigned long virt,
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phys_addr_t size, pgprot_t prot);
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extern void create_pgd_mapping(struct mm_struct *mm, phys_addr_t phys,
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unsigned long virt, phys_addr_t size,
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pgprot_t prot, bool page_mappings_only);
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extern void *fixmap_remap_fdt(phys_addr_t dt_phys, int *size, pgprot_t prot);
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extern void mark_linear_text_alias_ro(void);
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/*
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* This check is triggered during the early boot before the cpufeature
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* is initialised. Checking the status on the local CPU allows the boot
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* CPU to detect the need for non-global mappings and thus avoiding a
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* pagetable re-write after all the CPUs are booted. This check will be
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* anyway run on individual CPUs, allowing us to get the consistent
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* state once the SMP CPUs are up and thus make the switch to non-global
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* mappings if required.
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*/
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static inline bool kaslr_requires_kpti(void)
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{
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/*
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* E0PD does a similar job to KPTI so can be used instead
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* where available.
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*/
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if (IS_ENABLED(CONFIG_ARM64_E0PD)) {
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u64 mmfr2 = read_sysreg_s(SYS_ID_AA64MMFR2_EL1);
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if (cpuid_feature_extract_unsigned_field(mmfr2,
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ID_AA64MMFR2_EL1_E0PD_SHIFT))
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return false;
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}
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/*
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* Systems affected by Cavium erratum 24756 are incompatible
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* with KPTI.
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*/
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if (IS_ENABLED(CONFIG_CAVIUM_ERRATUM_27456)) {
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extern const struct midr_range cavium_erratum_27456_cpus[];
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if (is_midr_in_range_list(read_cpuid_id(),
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cavium_erratum_27456_cpus))
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return false;
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}
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return true;
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}
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#define INIT_MM_CONTEXT(name) \
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.pgd = swapper_pg_dir,
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#endif /* !__ASSEMBLY__ */
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#endif
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