1117 lines
27 KiB
C
1117 lines
27 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Alchemy clocks.
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*
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* Exposes all configurable internal clock sources to the clk framework.
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*
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* We have:
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* - Root source, usually 12MHz supplied by an external crystal
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* - 3 PLLs which generate multiples of root rate [AUX, CPU, AUX2]
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*
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* Dividers:
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* - 6 clock dividers with:
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* * selectable source [one of the PLLs],
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* * output divided between [2 .. 512 in steps of 2] (!Au1300)
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* or [1 .. 256 in steps of 1] (Au1300),
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* * can be enabled individually.
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*
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* - up to 6 "internal" (fixed) consumers which:
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* * take either AUXPLL or one of the above 6 dividers as input,
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* * divide this input by 1, 2, or 4 (and 3 on Au1300).
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* * can be disabled separately.
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*
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* Misc clocks:
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* - sysbus clock: CPU core clock (CPUPLL) divided by 2, 3 or 4.
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* depends on board design and should be set by bootloader, read-only.
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* - peripheral clock: half the rate of sysbus clock, source for a lot
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* of peripheral blocks, read-only.
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* - memory clock: clk rate to main memory chips, depends on board
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* design and is read-only,
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* - lrclk: the static bus clock signal for synchronous operation.
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* depends on board design, must be set by bootloader,
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* but may be required to correctly configure devices attached to
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* the static bus. The Au1000/1500/1100 manuals call it LCLK, on
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* later models it's called RCLK.
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#include <asm/mach-au1x00/au1000.h>
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/* Base clock: 12MHz is the default in all databooks, and I haven't
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* found any board yet which uses a different rate.
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*/
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#define ALCHEMY_ROOTCLK_RATE 12000000
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/*
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* the internal sources which can be driven by the PLLs and dividers.
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* Names taken from the databooks, refer to them for more information,
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* especially which ones are share a clock line.
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*/
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static const char * const alchemy_au1300_intclknames[] = {
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"lcd_intclk", "gpemgp_clk", "maempe_clk", "maebsa_clk",
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"EXTCLK0", "EXTCLK1"
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};
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static const char * const alchemy_au1200_intclknames[] = {
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"lcd_intclk", NULL, NULL, NULL, "EXTCLK0", "EXTCLK1"
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};
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static const char * const alchemy_au1550_intclknames[] = {
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"usb_clk", "psc0_intclk", "psc1_intclk", "pci_clko",
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"EXTCLK0", "EXTCLK1"
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};
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static const char * const alchemy_au1100_intclknames[] = {
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"usb_clk", "lcd_intclk", NULL, "i2s_clk", "EXTCLK0", "EXTCLK1"
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};
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static const char * const alchemy_au1500_intclknames[] = {
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NULL, "usbd_clk", "usbh_clk", "pci_clko", "EXTCLK0", "EXTCLK1"
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};
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static const char * const alchemy_au1000_intclknames[] = {
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"irda_clk", "usbd_clk", "usbh_clk", "i2s_clk", "EXTCLK0",
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"EXTCLK1"
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};
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/* aliases for a few on-chip sources which are either shared
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* or have gone through name changes.
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*/
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static struct clk_aliastable {
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char *alias;
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char *base;
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int cputype;
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} alchemy_clk_aliases[] __initdata = {
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{ "usbh_clk", "usb_clk", ALCHEMY_CPU_AU1100 },
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{ "usbd_clk", "usb_clk", ALCHEMY_CPU_AU1100 },
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{ "irda_clk", "usb_clk", ALCHEMY_CPU_AU1100 },
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{ "usbh_clk", "usb_clk", ALCHEMY_CPU_AU1550 },
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{ "usbd_clk", "usb_clk", ALCHEMY_CPU_AU1550 },
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{ "psc2_intclk", "usb_clk", ALCHEMY_CPU_AU1550 },
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{ "psc3_intclk", "EXTCLK0", ALCHEMY_CPU_AU1550 },
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{ "psc0_intclk", "EXTCLK0", ALCHEMY_CPU_AU1200 },
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{ "psc1_intclk", "EXTCLK1", ALCHEMY_CPU_AU1200 },
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{ "psc0_intclk", "EXTCLK0", ALCHEMY_CPU_AU1300 },
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{ "psc2_intclk", "EXTCLK0", ALCHEMY_CPU_AU1300 },
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{ "psc1_intclk", "EXTCLK1", ALCHEMY_CPU_AU1300 },
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{ "psc3_intclk", "EXTCLK1", ALCHEMY_CPU_AU1300 },
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{ NULL, NULL, 0 },
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};
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#define IOMEM(x) ((void __iomem *)(KSEG1ADDR(CPHYSADDR(x))))
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/* access locks to SYS_FREQCTRL0/1 and SYS_CLKSRC registers */
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static spinlock_t alchemy_clk_fg0_lock;
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static spinlock_t alchemy_clk_fg1_lock;
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static DEFINE_SPINLOCK(alchemy_clk_csrc_lock);
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/* CPU Core clock *****************************************************/
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static unsigned long alchemy_clk_cpu_recalc(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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unsigned long t;
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/*
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* On early Au1000, sys_cpupll was write-only. Since these
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* silicon versions of Au1000 are not sold, we don't bend
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* over backwards trying to determine the frequency.
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*/
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if (unlikely(au1xxx_cpu_has_pll_wo()))
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t = 396000000;
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else {
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t = alchemy_rdsys(AU1000_SYS_CPUPLL) & 0x7f;
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if (alchemy_get_cputype() < ALCHEMY_CPU_AU1300)
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t &= 0x3f;
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t *= parent_rate;
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}
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return t;
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}
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void __init alchemy_set_lpj(void)
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{
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preset_lpj = alchemy_clk_cpu_recalc(NULL, ALCHEMY_ROOTCLK_RATE);
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preset_lpj /= 2 * HZ;
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}
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static const struct clk_ops alchemy_clkops_cpu = {
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.recalc_rate = alchemy_clk_cpu_recalc,
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};
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static struct clk __init *alchemy_clk_setup_cpu(const char *parent_name,
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int ctype)
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{
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struct clk_init_data id;
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struct clk_hw *h;
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struct clk *clk;
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h = kzalloc(sizeof(*h), GFP_KERNEL);
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if (!h)
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return ERR_PTR(-ENOMEM);
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id.name = ALCHEMY_CPU_CLK;
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id.parent_names = &parent_name;
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id.num_parents = 1;
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id.flags = 0;
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id.ops = &alchemy_clkops_cpu;
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h->init = &id;
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clk = clk_register(NULL, h);
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if (IS_ERR(clk)) {
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pr_err("failed to register clock\n");
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kfree(h);
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}
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return clk;
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}
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/* AUXPLLs ************************************************************/
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struct alchemy_auxpll_clk {
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struct clk_hw hw;
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unsigned long reg; /* au1300 has also AUXPLL2 */
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int maxmult; /* max multiplier */
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};
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#define to_auxpll_clk(x) container_of(x, struct alchemy_auxpll_clk, hw)
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static unsigned long alchemy_clk_aux_recalc(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct alchemy_auxpll_clk *a = to_auxpll_clk(hw);
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return (alchemy_rdsys(a->reg) & 0xff) * parent_rate;
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}
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static int alchemy_clk_aux_setr(struct clk_hw *hw,
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unsigned long rate,
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unsigned long parent_rate)
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{
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struct alchemy_auxpll_clk *a = to_auxpll_clk(hw);
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unsigned long d = rate;
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if (rate)
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d /= parent_rate;
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else
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d = 0;
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/* minimum is 84MHz, max is 756-1032 depending on variant */
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if (((d < 7) && (d != 0)) || (d > a->maxmult))
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return -EINVAL;
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alchemy_wrsys(d, a->reg);
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return 0;
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}
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static long alchemy_clk_aux_roundr(struct clk_hw *hw,
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unsigned long rate,
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unsigned long *parent_rate)
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{
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struct alchemy_auxpll_clk *a = to_auxpll_clk(hw);
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unsigned long mult;
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if (!rate || !*parent_rate)
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return 0;
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mult = rate / (*parent_rate);
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if (mult && (mult < 7))
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mult = 7;
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if (mult > a->maxmult)
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mult = a->maxmult;
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return (*parent_rate) * mult;
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}
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static const struct clk_ops alchemy_clkops_aux = {
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.recalc_rate = alchemy_clk_aux_recalc,
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.set_rate = alchemy_clk_aux_setr,
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.round_rate = alchemy_clk_aux_roundr,
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};
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static struct clk __init *alchemy_clk_setup_aux(const char *parent_name,
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char *name, int maxmult,
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unsigned long reg)
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{
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struct clk_init_data id;
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struct clk *c;
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struct alchemy_auxpll_clk *a;
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a = kzalloc(sizeof(*a), GFP_KERNEL);
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if (!a)
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return ERR_PTR(-ENOMEM);
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id.name = name;
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id.parent_names = &parent_name;
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id.num_parents = 1;
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id.flags = CLK_GET_RATE_NOCACHE;
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id.ops = &alchemy_clkops_aux;
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a->reg = reg;
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a->maxmult = maxmult;
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a->hw.init = &id;
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c = clk_register(NULL, &a->hw);
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if (!IS_ERR(c))
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clk_register_clkdev(c, name, NULL);
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else
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kfree(a);
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return c;
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}
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/* sysbus_clk *********************************************************/
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static struct clk __init *alchemy_clk_setup_sysbus(const char *pn)
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{
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unsigned long v = (alchemy_rdsys(AU1000_SYS_POWERCTRL) & 3) + 2;
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struct clk *c;
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c = clk_register_fixed_factor(NULL, ALCHEMY_SYSBUS_CLK,
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pn, 0, 1, v);
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if (!IS_ERR(c))
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clk_register_clkdev(c, ALCHEMY_SYSBUS_CLK, NULL);
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return c;
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}
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/* Peripheral Clock ***************************************************/
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static struct clk __init *alchemy_clk_setup_periph(const char *pn)
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{
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/* Peripheral clock runs at half the rate of sysbus clk */
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struct clk *c;
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c = clk_register_fixed_factor(NULL, ALCHEMY_PERIPH_CLK,
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pn, 0, 1, 2);
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if (!IS_ERR(c))
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clk_register_clkdev(c, ALCHEMY_PERIPH_CLK, NULL);
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return c;
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}
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/* mem clock **********************************************************/
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static struct clk __init *alchemy_clk_setup_mem(const char *pn, int ct)
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{
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void __iomem *addr = IOMEM(AU1000_MEM_PHYS_ADDR);
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unsigned long v;
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struct clk *c;
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int div;
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switch (ct) {
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case ALCHEMY_CPU_AU1550:
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case ALCHEMY_CPU_AU1200:
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v = __raw_readl(addr + AU1550_MEM_SDCONFIGB);
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div = (v & (1 << 15)) ? 1 : 2;
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break;
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case ALCHEMY_CPU_AU1300:
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v = __raw_readl(addr + AU1550_MEM_SDCONFIGB);
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div = (v & (1 << 31)) ? 1 : 2;
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break;
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case ALCHEMY_CPU_AU1000:
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case ALCHEMY_CPU_AU1500:
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case ALCHEMY_CPU_AU1100:
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default:
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div = 2;
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break;
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}
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c = clk_register_fixed_factor(NULL, ALCHEMY_MEM_CLK, pn,
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0, 1, div);
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if (!IS_ERR(c))
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clk_register_clkdev(c, ALCHEMY_MEM_CLK, NULL);
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return c;
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}
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/* lrclk: external synchronous static bus clock ***********************/
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static struct clk __init *alchemy_clk_setup_lrclk(const char *pn, int t)
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{
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/* Au1000, Au1500: MEM_STCFG0[11]: If bit is set, lrclk=pclk/5,
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* otherwise lrclk=pclk/4.
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* All other variants: MEM_STCFG0[15:13] = divisor.
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* L/RCLK = periph_clk / (divisor + 1)
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* On Au1000, Au1500, Au1100 it's called LCLK,
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* on later models it's called RCLK, but it's the same thing.
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*/
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struct clk *c;
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unsigned long v = alchemy_rdsmem(AU1000_MEM_STCFG0);
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switch (t) {
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case ALCHEMY_CPU_AU1000:
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case ALCHEMY_CPU_AU1500:
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v = 4 + ((v >> 11) & 1);
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break;
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default: /* all other models */
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v = ((v >> 13) & 7) + 1;
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}
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c = clk_register_fixed_factor(NULL, ALCHEMY_LR_CLK,
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pn, 0, 1, v);
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if (!IS_ERR(c))
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clk_register_clkdev(c, ALCHEMY_LR_CLK, NULL);
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return c;
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}
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/* Clock dividers and muxes *******************************************/
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/* data for fgen and csrc mux-dividers */
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struct alchemy_fgcs_clk {
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struct clk_hw hw;
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spinlock_t *reglock; /* register lock */
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unsigned long reg; /* SYS_FREQCTRL0/1 */
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int shift; /* offset in register */
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int parent; /* parent before disable [Au1300] */
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int isen; /* is it enabled? */
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int *dt; /* dividertable for csrc */
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};
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#define to_fgcs_clk(x) container_of(x, struct alchemy_fgcs_clk, hw)
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static long alchemy_calc_div(unsigned long rate, unsigned long prate,
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int scale, int maxdiv, unsigned long *rv)
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{
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long div1, div2;
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div1 = prate / rate;
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if ((prate / div1) > rate)
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div1++;
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if (scale == 2) { /* only div-by-multiple-of-2 possible */
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if (div1 & 1)
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div1++; /* stay <=prate */
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}
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div2 = (div1 / scale) - 1; /* value to write to register */
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if (div2 > maxdiv)
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div2 = maxdiv;
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if (rv)
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*rv = div2;
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div1 = ((div2 + 1) * scale);
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return div1;
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}
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static int alchemy_clk_fgcs_detr(struct clk_hw *hw,
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struct clk_rate_request *req,
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int scale, int maxdiv)
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{
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struct clk_hw *pc, *bpc, *free;
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long tdv, tpr, pr, nr, br, bpr, diff, lastdiff;
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int j;
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lastdiff = INT_MAX;
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bpr = 0;
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bpc = NULL;
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br = -EINVAL;
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free = NULL;
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/* look at the rates each enabled parent supplies and select
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* the one that gets closest to but not over the requested rate.
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*/
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for (j = 0; j < 7; j++) {
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pc = clk_hw_get_parent_by_index(hw, j);
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if (!pc)
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break;
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/* if this parent is currently unused, remember it.
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* XXX: we would actually want clk_has_active_children()
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* but this is a good-enough approximation for now.
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*/
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if (!clk_hw_is_prepared(pc)) {
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if (!free)
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free = pc;
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}
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pr = clk_hw_get_rate(pc);
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if (pr < req->rate)
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continue;
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/* what can hardware actually provide */
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tdv = alchemy_calc_div(req->rate, pr, scale, maxdiv, NULL);
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nr = pr / tdv;
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diff = req->rate - nr;
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if (nr > req->rate)
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continue;
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if (diff < lastdiff) {
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lastdiff = diff;
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bpr = pr;
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bpc = pc;
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br = nr;
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}
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if (diff == 0)
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break;
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}
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/* if we couldn't get the exact rate we wanted from the enabled
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* parents, maybe we can tell an available disabled/inactive one
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* to give us a rate we can divide down to the requested rate.
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*/
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if (lastdiff && free) {
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for (j = (maxdiv == 4) ? 1 : scale; j <= maxdiv; j += scale) {
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tpr = req->rate * j;
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if (tpr < 0)
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break;
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pr = clk_hw_round_rate(free, tpr);
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tdv = alchemy_calc_div(req->rate, pr, scale, maxdiv,
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NULL);
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nr = pr / tdv;
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diff = req->rate - nr;
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if (nr > req->rate)
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continue;
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if (diff < lastdiff) {
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lastdiff = diff;
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bpr = pr;
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bpc = free;
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br = nr;
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}
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if (diff == 0)
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break;
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}
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}
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if (br < 0)
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return br;
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req->best_parent_rate = bpr;
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req->best_parent_hw = bpc;
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req->rate = br;
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return 0;
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}
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static int alchemy_clk_fgv1_en(struct clk_hw *hw)
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{
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struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
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unsigned long v, flags;
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spin_lock_irqsave(c->reglock, flags);
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v = alchemy_rdsys(c->reg);
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v |= (1 << 1) << c->shift;
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alchemy_wrsys(v, c->reg);
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spin_unlock_irqrestore(c->reglock, flags);
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return 0;
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}
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static int alchemy_clk_fgv1_isen(struct clk_hw *hw)
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{
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struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
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|
unsigned long v = alchemy_rdsys(c->reg) >> (c->shift + 1);
|
|
|
|
return v & 1;
|
|
}
|
|
|
|
static void alchemy_clk_fgv1_dis(struct clk_hw *hw)
|
|
{
|
|
struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
|
|
unsigned long v, flags;
|
|
|
|
spin_lock_irqsave(c->reglock, flags);
|
|
v = alchemy_rdsys(c->reg);
|
|
v &= ~((1 << 1) << c->shift);
|
|
alchemy_wrsys(v, c->reg);
|
|
spin_unlock_irqrestore(c->reglock, flags);
|
|
}
|
|
|
|
static int alchemy_clk_fgv1_setp(struct clk_hw *hw, u8 index)
|
|
{
|
|
struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
|
|
unsigned long v, flags;
|
|
|
|
spin_lock_irqsave(c->reglock, flags);
|
|
v = alchemy_rdsys(c->reg);
|
|
if (index)
|
|
v |= (1 << c->shift);
|
|
else
|
|
v &= ~(1 << c->shift);
|
|
alchemy_wrsys(v, c->reg);
|
|
spin_unlock_irqrestore(c->reglock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static u8 alchemy_clk_fgv1_getp(struct clk_hw *hw)
|
|
{
|
|
struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
|
|
|
|
return (alchemy_rdsys(c->reg) >> c->shift) & 1;
|
|
}
|
|
|
|
static int alchemy_clk_fgv1_setr(struct clk_hw *hw, unsigned long rate,
|
|
unsigned long parent_rate)
|
|
{
|
|
struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
|
|
unsigned long div, v, flags, ret;
|
|
int sh = c->shift + 2;
|
|
|
|
if (!rate || !parent_rate || rate > (parent_rate / 2))
|
|
return -EINVAL;
|
|
ret = alchemy_calc_div(rate, parent_rate, 2, 512, &div);
|
|
spin_lock_irqsave(c->reglock, flags);
|
|
v = alchemy_rdsys(c->reg);
|
|
v &= ~(0xff << sh);
|
|
v |= div << sh;
|
|
alchemy_wrsys(v, c->reg);
|
|
spin_unlock_irqrestore(c->reglock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static unsigned long alchemy_clk_fgv1_recalc(struct clk_hw *hw,
|
|
unsigned long parent_rate)
|
|
{
|
|
struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
|
|
unsigned long v = alchemy_rdsys(c->reg) >> (c->shift + 2);
|
|
|
|
v = ((v & 0xff) + 1) * 2;
|
|
return parent_rate / v;
|
|
}
|
|
|
|
static int alchemy_clk_fgv1_detr(struct clk_hw *hw,
|
|
struct clk_rate_request *req)
|
|
{
|
|
return alchemy_clk_fgcs_detr(hw, req, 2, 512);
|
|
}
|
|
|
|
/* Au1000, Au1100, Au15x0, Au12x0 */
|
|
static const struct clk_ops alchemy_clkops_fgenv1 = {
|
|
.recalc_rate = alchemy_clk_fgv1_recalc,
|
|
.determine_rate = alchemy_clk_fgv1_detr,
|
|
.set_rate = alchemy_clk_fgv1_setr,
|
|
.set_parent = alchemy_clk_fgv1_setp,
|
|
.get_parent = alchemy_clk_fgv1_getp,
|
|
.enable = alchemy_clk_fgv1_en,
|
|
.disable = alchemy_clk_fgv1_dis,
|
|
.is_enabled = alchemy_clk_fgv1_isen,
|
|
};
|
|
|
|
static void __alchemy_clk_fgv2_en(struct alchemy_fgcs_clk *c)
|
|
{
|
|
unsigned long v = alchemy_rdsys(c->reg);
|
|
|
|
v &= ~(3 << c->shift);
|
|
v |= (c->parent & 3) << c->shift;
|
|
alchemy_wrsys(v, c->reg);
|
|
c->isen = 1;
|
|
}
|
|
|
|
static int alchemy_clk_fgv2_en(struct clk_hw *hw)
|
|
{
|
|
struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
|
|
unsigned long flags;
|
|
|
|
/* enable by setting the previous parent clock */
|
|
spin_lock_irqsave(c->reglock, flags);
|
|
__alchemy_clk_fgv2_en(c);
|
|
spin_unlock_irqrestore(c->reglock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int alchemy_clk_fgv2_isen(struct clk_hw *hw)
|
|
{
|
|
struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
|
|
|
|
return ((alchemy_rdsys(c->reg) >> c->shift) & 3) != 0;
|
|
}
|
|
|
|
static void alchemy_clk_fgv2_dis(struct clk_hw *hw)
|
|
{
|
|
struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
|
|
unsigned long v, flags;
|
|
|
|
spin_lock_irqsave(c->reglock, flags);
|
|
v = alchemy_rdsys(c->reg);
|
|
v &= ~(3 << c->shift); /* set input mux to "disabled" state */
|
|
alchemy_wrsys(v, c->reg);
|
|
c->isen = 0;
|
|
spin_unlock_irqrestore(c->reglock, flags);
|
|
}
|
|
|
|
static int alchemy_clk_fgv2_setp(struct clk_hw *hw, u8 index)
|
|
{
|
|
struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(c->reglock, flags);
|
|
c->parent = index + 1; /* value to write to register */
|
|
if (c->isen)
|
|
__alchemy_clk_fgv2_en(c);
|
|
spin_unlock_irqrestore(c->reglock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static u8 alchemy_clk_fgv2_getp(struct clk_hw *hw)
|
|
{
|
|
struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
|
|
unsigned long flags, v;
|
|
|
|
spin_lock_irqsave(c->reglock, flags);
|
|
v = c->parent - 1;
|
|
spin_unlock_irqrestore(c->reglock, flags);
|
|
return v;
|
|
}
|
|
|
|
/* fg0-2 and fg4-6 share a "scale"-bit. With this bit cleared, the
|
|
* dividers behave exactly as on previous models (dividers are multiples
|
|
* of 2); with the bit set, dividers are multiples of 1, halving their
|
|
* range, but making them also much more flexible.
|
|
*/
|
|
static int alchemy_clk_fgv2_setr(struct clk_hw *hw, unsigned long rate,
|
|
unsigned long parent_rate)
|
|
{
|
|
struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
|
|
int sh = c->shift + 2;
|
|
unsigned long div, v, flags, ret;
|
|
|
|
if (!rate || !parent_rate || rate > parent_rate)
|
|
return -EINVAL;
|
|
|
|
v = alchemy_rdsys(c->reg) & (1 << 30); /* test "scale" bit */
|
|
ret = alchemy_calc_div(rate, parent_rate, v ? 1 : 2,
|
|
v ? 256 : 512, &div);
|
|
|
|
spin_lock_irqsave(c->reglock, flags);
|
|
v = alchemy_rdsys(c->reg);
|
|
v &= ~(0xff << sh);
|
|
v |= (div & 0xff) << sh;
|
|
alchemy_wrsys(v, c->reg);
|
|
spin_unlock_irqrestore(c->reglock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static unsigned long alchemy_clk_fgv2_recalc(struct clk_hw *hw,
|
|
unsigned long parent_rate)
|
|
{
|
|
struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
|
|
int sh = c->shift + 2;
|
|
unsigned long v, t;
|
|
|
|
v = alchemy_rdsys(c->reg);
|
|
t = parent_rate / (((v >> sh) & 0xff) + 1);
|
|
if ((v & (1 << 30)) == 0) /* test scale bit */
|
|
t /= 2;
|
|
|
|
return t;
|
|
}
|
|
|
|
static int alchemy_clk_fgv2_detr(struct clk_hw *hw,
|
|
struct clk_rate_request *req)
|
|
{
|
|
struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
|
|
int scale, maxdiv;
|
|
|
|
if (alchemy_rdsys(c->reg) & (1 << 30)) {
|
|
scale = 1;
|
|
maxdiv = 256;
|
|
} else {
|
|
scale = 2;
|
|
maxdiv = 512;
|
|
}
|
|
|
|
return alchemy_clk_fgcs_detr(hw, req, scale, maxdiv);
|
|
}
|
|
|
|
/* Au1300 larger input mux, no separate disable bit, flexible divider */
|
|
static const struct clk_ops alchemy_clkops_fgenv2 = {
|
|
.recalc_rate = alchemy_clk_fgv2_recalc,
|
|
.determine_rate = alchemy_clk_fgv2_detr,
|
|
.set_rate = alchemy_clk_fgv2_setr,
|
|
.set_parent = alchemy_clk_fgv2_setp,
|
|
.get_parent = alchemy_clk_fgv2_getp,
|
|
.enable = alchemy_clk_fgv2_en,
|
|
.disable = alchemy_clk_fgv2_dis,
|
|
.is_enabled = alchemy_clk_fgv2_isen,
|
|
};
|
|
|
|
static const char * const alchemy_clk_fgv1_parents[] = {
|
|
ALCHEMY_CPU_CLK, ALCHEMY_AUXPLL_CLK
|
|
};
|
|
|
|
static const char * const alchemy_clk_fgv2_parents[] = {
|
|
ALCHEMY_AUXPLL2_CLK, ALCHEMY_CPU_CLK, ALCHEMY_AUXPLL_CLK
|
|
};
|
|
|
|
static const char * const alchemy_clk_fgen_names[] = {
|
|
ALCHEMY_FG0_CLK, ALCHEMY_FG1_CLK, ALCHEMY_FG2_CLK,
|
|
ALCHEMY_FG3_CLK, ALCHEMY_FG4_CLK, ALCHEMY_FG5_CLK };
|
|
|
|
static int __init alchemy_clk_init_fgens(int ctype)
|
|
{
|
|
struct clk *c;
|
|
struct clk_init_data id;
|
|
struct alchemy_fgcs_clk *a;
|
|
unsigned long v;
|
|
int i, ret;
|
|
|
|
switch (ctype) {
|
|
case ALCHEMY_CPU_AU1000...ALCHEMY_CPU_AU1200:
|
|
id.ops = &alchemy_clkops_fgenv1;
|
|
id.parent_names = alchemy_clk_fgv1_parents;
|
|
id.num_parents = 2;
|
|
break;
|
|
case ALCHEMY_CPU_AU1300:
|
|
id.ops = &alchemy_clkops_fgenv2;
|
|
id.parent_names = alchemy_clk_fgv2_parents;
|
|
id.num_parents = 3;
|
|
break;
|
|
default:
|
|
return -ENODEV;
|
|
}
|
|
id.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE;
|
|
|
|
a = kcalloc(6, sizeof(*a), GFP_KERNEL);
|
|
if (!a)
|
|
return -ENOMEM;
|
|
|
|
spin_lock_init(&alchemy_clk_fg0_lock);
|
|
spin_lock_init(&alchemy_clk_fg1_lock);
|
|
ret = 0;
|
|
for (i = 0; i < 6; i++) {
|
|
id.name = alchemy_clk_fgen_names[i];
|
|
a->shift = 10 * (i < 3 ? i : i - 3);
|
|
if (i > 2) {
|
|
a->reg = AU1000_SYS_FREQCTRL1;
|
|
a->reglock = &alchemy_clk_fg1_lock;
|
|
} else {
|
|
a->reg = AU1000_SYS_FREQCTRL0;
|
|
a->reglock = &alchemy_clk_fg0_lock;
|
|
}
|
|
|
|
/* default to first parent if bootloader has set
|
|
* the mux to disabled state.
|
|
*/
|
|
if (ctype == ALCHEMY_CPU_AU1300) {
|
|
v = alchemy_rdsys(a->reg);
|
|
a->parent = (v >> a->shift) & 3;
|
|
if (!a->parent) {
|
|
a->parent = 1;
|
|
a->isen = 0;
|
|
} else
|
|
a->isen = 1;
|
|
}
|
|
|
|
a->hw.init = &id;
|
|
c = clk_register(NULL, &a->hw);
|
|
if (IS_ERR(c))
|
|
ret++;
|
|
else
|
|
clk_register_clkdev(c, id.name, NULL);
|
|
a++;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
/* internal sources muxes *********************************************/
|
|
|
|
static int alchemy_clk_csrc_isen(struct clk_hw *hw)
|
|
{
|
|
struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
|
|
unsigned long v = alchemy_rdsys(c->reg);
|
|
|
|
return (((v >> c->shift) >> 2) & 7) != 0;
|
|
}
|
|
|
|
static void __alchemy_clk_csrc_en(struct alchemy_fgcs_clk *c)
|
|
{
|
|
unsigned long v = alchemy_rdsys(c->reg);
|
|
|
|
v &= ~((7 << 2) << c->shift);
|
|
v |= ((c->parent & 7) << 2) << c->shift;
|
|
alchemy_wrsys(v, c->reg);
|
|
c->isen = 1;
|
|
}
|
|
|
|
static int alchemy_clk_csrc_en(struct clk_hw *hw)
|
|
{
|
|
struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
|
|
unsigned long flags;
|
|
|
|
/* enable by setting the previous parent clock */
|
|
spin_lock_irqsave(c->reglock, flags);
|
|
__alchemy_clk_csrc_en(c);
|
|
spin_unlock_irqrestore(c->reglock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void alchemy_clk_csrc_dis(struct clk_hw *hw)
|
|
{
|
|
struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
|
|
unsigned long v, flags;
|
|
|
|
spin_lock_irqsave(c->reglock, flags);
|
|
v = alchemy_rdsys(c->reg);
|
|
v &= ~((3 << 2) << c->shift); /* mux to "disabled" state */
|
|
alchemy_wrsys(v, c->reg);
|
|
c->isen = 0;
|
|
spin_unlock_irqrestore(c->reglock, flags);
|
|
}
|
|
|
|
static int alchemy_clk_csrc_setp(struct clk_hw *hw, u8 index)
|
|
{
|
|
struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(c->reglock, flags);
|
|
c->parent = index + 1; /* value to write to register */
|
|
if (c->isen)
|
|
__alchemy_clk_csrc_en(c);
|
|
spin_unlock_irqrestore(c->reglock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static u8 alchemy_clk_csrc_getp(struct clk_hw *hw)
|
|
{
|
|
struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
|
|
|
|
return c->parent - 1;
|
|
}
|
|
|
|
static unsigned long alchemy_clk_csrc_recalc(struct clk_hw *hw,
|
|
unsigned long parent_rate)
|
|
{
|
|
struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
|
|
unsigned long v = (alchemy_rdsys(c->reg) >> c->shift) & 3;
|
|
|
|
return parent_rate / c->dt[v];
|
|
}
|
|
|
|
static int alchemy_clk_csrc_setr(struct clk_hw *hw, unsigned long rate,
|
|
unsigned long parent_rate)
|
|
{
|
|
struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
|
|
unsigned long d, v, flags;
|
|
int i;
|
|
|
|
if (!rate || !parent_rate || rate > parent_rate)
|
|
return -EINVAL;
|
|
|
|
d = (parent_rate + (rate / 2)) / rate;
|
|
if (d > 4)
|
|
return -EINVAL;
|
|
if ((d == 3) && (c->dt[2] != 3))
|
|
d = 4;
|
|
|
|
for (i = 0; i < 4; i++)
|
|
if (c->dt[i] == d)
|
|
break;
|
|
|
|
if (i >= 4)
|
|
return -EINVAL; /* oops */
|
|
|
|
spin_lock_irqsave(c->reglock, flags);
|
|
v = alchemy_rdsys(c->reg);
|
|
v &= ~(3 << c->shift);
|
|
v |= (i & 3) << c->shift;
|
|
alchemy_wrsys(v, c->reg);
|
|
spin_unlock_irqrestore(c->reglock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int alchemy_clk_csrc_detr(struct clk_hw *hw,
|
|
struct clk_rate_request *req)
|
|
{
|
|
struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
|
|
int scale = c->dt[2] == 3 ? 1 : 2; /* au1300 check */
|
|
|
|
return alchemy_clk_fgcs_detr(hw, req, scale, 4);
|
|
}
|
|
|
|
static const struct clk_ops alchemy_clkops_csrc = {
|
|
.recalc_rate = alchemy_clk_csrc_recalc,
|
|
.determine_rate = alchemy_clk_csrc_detr,
|
|
.set_rate = alchemy_clk_csrc_setr,
|
|
.set_parent = alchemy_clk_csrc_setp,
|
|
.get_parent = alchemy_clk_csrc_getp,
|
|
.enable = alchemy_clk_csrc_en,
|
|
.disable = alchemy_clk_csrc_dis,
|
|
.is_enabled = alchemy_clk_csrc_isen,
|
|
};
|
|
|
|
static const char * const alchemy_clk_csrc_parents[] = {
|
|
/* disabled at index 0 */ ALCHEMY_AUXPLL_CLK,
|
|
ALCHEMY_FG0_CLK, ALCHEMY_FG1_CLK, ALCHEMY_FG2_CLK,
|
|
ALCHEMY_FG3_CLK, ALCHEMY_FG4_CLK, ALCHEMY_FG5_CLK
|
|
};
|
|
|
|
/* divider tables */
|
|
static int alchemy_csrc_dt1[] = { 1, 4, 1, 2 }; /* rest */
|
|
static int alchemy_csrc_dt2[] = { 1, 4, 3, 2 }; /* Au1300 */
|
|
|
|
static int __init alchemy_clk_setup_imux(int ctype)
|
|
{
|
|
struct alchemy_fgcs_clk *a;
|
|
const char * const *names;
|
|
struct clk_init_data id;
|
|
unsigned long v;
|
|
int i, ret, *dt;
|
|
struct clk *c;
|
|
|
|
id.ops = &alchemy_clkops_csrc;
|
|
id.parent_names = alchemy_clk_csrc_parents;
|
|
id.num_parents = 7;
|
|
id.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE;
|
|
|
|
dt = alchemy_csrc_dt1;
|
|
switch (ctype) {
|
|
case ALCHEMY_CPU_AU1000:
|
|
names = alchemy_au1000_intclknames;
|
|
break;
|
|
case ALCHEMY_CPU_AU1500:
|
|
names = alchemy_au1500_intclknames;
|
|
break;
|
|
case ALCHEMY_CPU_AU1100:
|
|
names = alchemy_au1100_intclknames;
|
|
break;
|
|
case ALCHEMY_CPU_AU1550:
|
|
names = alchemy_au1550_intclknames;
|
|
break;
|
|
case ALCHEMY_CPU_AU1200:
|
|
names = alchemy_au1200_intclknames;
|
|
break;
|
|
case ALCHEMY_CPU_AU1300:
|
|
dt = alchemy_csrc_dt2;
|
|
names = alchemy_au1300_intclknames;
|
|
break;
|
|
default:
|
|
return -ENODEV;
|
|
}
|
|
|
|
a = kcalloc(6, sizeof(*a), GFP_KERNEL);
|
|
if (!a)
|
|
return -ENOMEM;
|
|
|
|
ret = 0;
|
|
|
|
for (i = 0; i < 6; i++) {
|
|
id.name = names[i];
|
|
if (!id.name)
|
|
goto next;
|
|
|
|
a->shift = i * 5;
|
|
a->reg = AU1000_SYS_CLKSRC;
|
|
a->reglock = &alchemy_clk_csrc_lock;
|
|
a->dt = dt;
|
|
|
|
/* default to first parent clock if mux is initially
|
|
* set to disabled state.
|
|
*/
|
|
v = alchemy_rdsys(a->reg);
|
|
a->parent = ((v >> a->shift) >> 2) & 7;
|
|
if (!a->parent) {
|
|
a->parent = 1;
|
|
a->isen = 0;
|
|
} else
|
|
a->isen = 1;
|
|
|
|
a->hw.init = &id;
|
|
c = clk_register(NULL, &a->hw);
|
|
if (IS_ERR(c))
|
|
ret++;
|
|
else
|
|
clk_register_clkdev(c, id.name, NULL);
|
|
next:
|
|
a++;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
|
|
/**********************************************************************/
|
|
|
|
|
|
#define ERRCK(x) \
|
|
if (IS_ERR(x)) { \
|
|
ret = PTR_ERR(x); \
|
|
goto out; \
|
|
}
|
|
|
|
static int __init alchemy_clk_init(void)
|
|
{
|
|
int ctype = alchemy_get_cputype(), ret, i;
|
|
struct clk_aliastable *t = alchemy_clk_aliases;
|
|
struct clk *c;
|
|
|
|
/* Root of the Alchemy clock tree: external 12MHz crystal osc */
|
|
c = clk_register_fixed_rate(NULL, ALCHEMY_ROOT_CLK, NULL,
|
|
0, ALCHEMY_ROOTCLK_RATE);
|
|
ERRCK(c)
|
|
|
|
/* CPU core clock */
|
|
c = alchemy_clk_setup_cpu(ALCHEMY_ROOT_CLK, ctype);
|
|
ERRCK(c)
|
|
|
|
/* AUXPLLs: max 1GHz on Au1300, 748MHz on older models */
|
|
i = (ctype == ALCHEMY_CPU_AU1300) ? 84 : 63;
|
|
c = alchemy_clk_setup_aux(ALCHEMY_ROOT_CLK, ALCHEMY_AUXPLL_CLK,
|
|
i, AU1000_SYS_AUXPLL);
|
|
ERRCK(c)
|
|
|
|
if (ctype == ALCHEMY_CPU_AU1300) {
|
|
c = alchemy_clk_setup_aux(ALCHEMY_ROOT_CLK,
|
|
ALCHEMY_AUXPLL2_CLK, i,
|
|
AU1300_SYS_AUXPLL2);
|
|
ERRCK(c)
|
|
}
|
|
|
|
/* sysbus clock: cpu core clock divided by 2, 3 or 4 */
|
|
c = alchemy_clk_setup_sysbus(ALCHEMY_CPU_CLK);
|
|
ERRCK(c)
|
|
|
|
/* peripheral clock: runs at half rate of sysbus clk */
|
|
c = alchemy_clk_setup_periph(ALCHEMY_SYSBUS_CLK);
|
|
ERRCK(c)
|
|
|
|
/* SDR/DDR memory clock */
|
|
c = alchemy_clk_setup_mem(ALCHEMY_SYSBUS_CLK, ctype);
|
|
ERRCK(c)
|
|
|
|
/* L/RCLK: external static bus clock for synchronous mode */
|
|
c = alchemy_clk_setup_lrclk(ALCHEMY_PERIPH_CLK, ctype);
|
|
ERRCK(c)
|
|
|
|
/* Frequency dividers 0-5 */
|
|
ret = alchemy_clk_init_fgens(ctype);
|
|
if (ret) {
|
|
ret = -ENODEV;
|
|
goto out;
|
|
}
|
|
|
|
/* diving muxes for internal sources */
|
|
ret = alchemy_clk_setup_imux(ctype);
|
|
if (ret) {
|
|
ret = -ENODEV;
|
|
goto out;
|
|
}
|
|
|
|
/* set up aliases drivers might look for */
|
|
while (t->base) {
|
|
if (t->cputype == ctype)
|
|
clk_add_alias(t->alias, NULL, t->base, NULL);
|
|
t++;
|
|
}
|
|
|
|
pr_info("Alchemy clocktree installed\n");
|
|
return 0;
|
|
|
|
out:
|
|
return ret;
|
|
}
|
|
postcore_initcall(alchemy_clk_init);
|