153 lines
3.6 KiB
C
153 lines
3.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* T1042 platform DIU operation
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*
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* Copyright 2014 Freescale Semiconductor Inc.
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <sysdev/fsl_soc.h>
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/*DIU Pixel ClockCR offset in scfg*/
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#define CCSR_SCFG_PIXCLKCR 0x28
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/* DIU Pixel Clock bits of the PIXCLKCR */
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#define PIXCLKCR_PXCKEN 0x80000000
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#define PIXCLKCR_PXCKINV 0x40000000
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#define PIXCLKCR_PXCKDLY 0x0000FF00
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#define PIXCLKCR_PXCLK_MASK 0x00FF0000
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/* Some CPLD register definitions */
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#define CPLD_DIUCSR 0x16
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#define CPLD_DIUCSR_DVIEN 0x80
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#define CPLD_DIUCSR_BACKLIGHT 0x0f
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struct device_node *cpld_node;
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/**
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* t1042rdb_set_monitor_port: switch the output to a different monitor port
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*/
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static void t1042rdb_set_monitor_port(enum fsl_diu_monitor_port port)
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{
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void __iomem *cpld_base;
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cpld_base = of_iomap(cpld_node, 0);
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if (!cpld_base) {
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pr_err("%s: Could not map cpld registers\n", __func__);
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goto exit;
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}
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switch (port) {
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case FSL_DIU_PORT_DVI:
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/* Enable the DVI(HDMI) port, disable the DFP and
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* the backlight
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*/
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clrbits8(cpld_base + CPLD_DIUCSR, CPLD_DIUCSR_DVIEN);
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break;
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case FSL_DIU_PORT_LVDS:
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/*
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* LVDS also needs backlight enabled, otherwise the display
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* will be blank.
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*/
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/* Enable the DFP port, disable the DVI*/
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setbits8(cpld_base + CPLD_DIUCSR, 0x01 << 8);
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setbits8(cpld_base + CPLD_DIUCSR, 0x01 << 4);
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setbits8(cpld_base + CPLD_DIUCSR, CPLD_DIUCSR_BACKLIGHT);
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break;
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default:
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pr_err("%s: Unsupported monitor port %i\n", __func__, port);
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}
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iounmap(cpld_base);
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exit:
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of_node_put(cpld_node);
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}
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/**
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* t1042rdb_set_pixel_clock: program the DIU's clock
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* @pixclock: pixel clock in ps (pico seconds)
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*/
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static void t1042rdb_set_pixel_clock(unsigned int pixclock)
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{
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struct device_node *scfg_np;
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void __iomem *scfg;
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unsigned long freq;
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u64 temp;
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u32 pxclk;
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scfg_np = of_find_compatible_node(NULL, NULL, "fsl,t1040-scfg");
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if (!scfg_np) {
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pr_err("%s: Missing scfg node. Can not display video.\n",
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__func__);
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return;
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}
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scfg = of_iomap(scfg_np, 0);
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of_node_put(scfg_np);
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if (!scfg) {
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pr_err("%s: Could not map device. Can not display video.\n",
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__func__);
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return;
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}
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/* Convert pixclock into frequency */
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temp = 1000000000000ULL;
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do_div(temp, pixclock);
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freq = temp;
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/*
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* 'pxclk' is the ratio of the platform clock to the pixel clock.
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* This number is programmed into the PIXCLKCR register, and the valid
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* range of values is 2-255.
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*/
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pxclk = DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq);
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pxclk = clamp_t(u32, pxclk, 2, 255);
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/* Disable the pixel clock, and set it to non-inverted and no delay */
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clrbits32(scfg + CCSR_SCFG_PIXCLKCR,
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PIXCLKCR_PXCKEN | PIXCLKCR_PXCKDLY | PIXCLKCR_PXCLK_MASK);
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/* Enable the clock and set the pxclk */
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setbits32(scfg + CCSR_SCFG_PIXCLKCR, PIXCLKCR_PXCKEN | (pxclk << 16));
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iounmap(scfg);
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}
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/**
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* t1042rdb_valid_monitor_port: set the monitor port for sysfs
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*/
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static enum fsl_diu_monitor_port
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t1042rdb_valid_monitor_port(enum fsl_diu_monitor_port port)
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{
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switch (port) {
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case FSL_DIU_PORT_DVI:
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case FSL_DIU_PORT_LVDS:
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return port;
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default:
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return FSL_DIU_PORT_DVI; /* Dual-link LVDS is not supported */
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}
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}
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static int __init t1042rdb_diu_init(void)
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{
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cpld_node = of_find_compatible_node(NULL, NULL, "fsl,t1042rdb-cpld");
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if (!cpld_node)
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return 0;
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diu_ops.set_monitor_port = t1042rdb_set_monitor_port;
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diu_ops.set_pixel_clock = t1042rdb_set_pixel_clock;
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diu_ops.valid_monitor_port = t1042rdb_valid_monitor_port;
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return 0;
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}
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early_initcall(t1042rdb_diu_init);
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MODULE_LICENSE("GPL");
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