Alexandre Ghiti 1d84afaf02 riscv: Fix fully ordered LR/SC xchg[8|16]() implementations ... The fully ordered versions of xchg[8|16]() using LR/SC lack the necessary memory barriers to guarantee the order. Fix this by matching what is already implemented in the fully ordered versions of cmpxchg() using LR/SC. Suggested-by: Andrea Parri <parri.andrea@gmail.com> Reported-by: Andrea Parri <parri.andrea@gmail.com> Closes: https://lore.kernel.org/linux-riscv/ZlYbupL5XgzgA0MX@andrea/T/#u Fixes: a8ed2b7a2c ("riscv/cmpxchg: Implement xchg for variables of size 1 and 2") Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> Reviewed-by: Andrea Parri <parri.andrea@gmail.com> Link: https://lore.kernel.org/r/20240530145546.394248-1-alexghiti@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>		2024-05-30 09:43:14 -07:00
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asm	riscv: Fix fully ordered LR/SC xchg[8|16]() implementations	2024-05-30 09:43:14 -07:00
uapi/asm	RISC-V Patches for the 6.10 Merge Window, Part 1	2024-05-22 09:56:00 -07:00