346 lines
8.4 KiB
C
346 lines
8.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2019 Linaro, Ltd. <ard.biesheuvel@linaro.org>
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*/
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#ifdef CONFIG_ARM64
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#include <asm/neon-intrinsics.h>
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#define AES_ROUND "aese %0.16b, %1.16b \n\t aesmc %0.16b, %0.16b"
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#else
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#include <arm_neon.h>
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#define AES_ROUND "aese.8 %q0, %q1 \n\t aesmc.8 %q0, %q0"
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#endif
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#define AEGIS_BLOCK_SIZE 16
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#include <stddef.h>
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#include "aegis-neon.h"
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extern int aegis128_have_aes_insn;
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void *memcpy(void *dest, const void *src, size_t n);
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struct aegis128_state {
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uint8x16_t v[5];
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};
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extern const uint8_t crypto_aes_sbox[];
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static struct aegis128_state aegis128_load_state_neon(const void *state)
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{
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return (struct aegis128_state){ {
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vld1q_u8(state),
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vld1q_u8(state + 16),
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vld1q_u8(state + 32),
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vld1q_u8(state + 48),
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vld1q_u8(state + 64)
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} };
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}
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static void aegis128_save_state_neon(struct aegis128_state st, void *state)
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{
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vst1q_u8(state, st.v[0]);
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vst1q_u8(state + 16, st.v[1]);
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vst1q_u8(state + 32, st.v[2]);
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vst1q_u8(state + 48, st.v[3]);
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vst1q_u8(state + 64, st.v[4]);
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}
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static inline __attribute__((always_inline))
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uint8x16_t aegis_aes_round(uint8x16_t w)
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{
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uint8x16_t z = {};
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#ifdef CONFIG_ARM64
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if (!__builtin_expect(aegis128_have_aes_insn, 1)) {
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static const uint8_t shift_rows[] = {
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0x0, 0x5, 0xa, 0xf, 0x4, 0x9, 0xe, 0x3,
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0x8, 0xd, 0x2, 0x7, 0xc, 0x1, 0x6, 0xb,
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};
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static const uint8_t ror32by8[] = {
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0x1, 0x2, 0x3, 0x0, 0x5, 0x6, 0x7, 0x4,
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0x9, 0xa, 0xb, 0x8, 0xd, 0xe, 0xf, 0xc,
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};
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uint8x16_t v;
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// shift rows
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w = vqtbl1q_u8(w, vld1q_u8(shift_rows));
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// sub bytes
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#ifndef CONFIG_CC_IS_GCC
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v = vqtbl4q_u8(vld1q_u8_x4(crypto_aes_sbox), w);
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v = vqtbx4q_u8(v, vld1q_u8_x4(crypto_aes_sbox + 0x40), w - 0x40);
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v = vqtbx4q_u8(v, vld1q_u8_x4(crypto_aes_sbox + 0x80), w - 0x80);
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v = vqtbx4q_u8(v, vld1q_u8_x4(crypto_aes_sbox + 0xc0), w - 0xc0);
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#else
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asm("tbl %0.16b, {v16.16b-v19.16b}, %1.16b" : "=w"(v) : "w"(w));
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w -= 0x40;
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asm("tbx %0.16b, {v20.16b-v23.16b}, %1.16b" : "+w"(v) : "w"(w));
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w -= 0x40;
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asm("tbx %0.16b, {v24.16b-v27.16b}, %1.16b" : "+w"(v) : "w"(w));
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w -= 0x40;
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asm("tbx %0.16b, {v28.16b-v31.16b}, %1.16b" : "+w"(v) : "w"(w));
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#endif
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// mix columns
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w = (v << 1) ^ (uint8x16_t)(((int8x16_t)v >> 7) & 0x1b);
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w ^= (uint8x16_t)vrev32q_u16((uint16x8_t)v);
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w ^= vqtbl1q_u8(v ^ w, vld1q_u8(ror32by8));
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return w;
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}
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#endif
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/*
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* We use inline asm here instead of the vaeseq_u8/vaesmcq_u8 intrinsics
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* to force the compiler to issue the aese/aesmc instructions in pairs.
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* This is much faster on many cores, where the instruction pair can
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* execute in a single cycle.
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*/
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asm(AES_ROUND : "+w"(w) : "w"(z));
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return w;
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}
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static inline __attribute__((always_inline))
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struct aegis128_state aegis128_update_neon(struct aegis128_state st,
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uint8x16_t m)
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{
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m ^= aegis_aes_round(st.v[4]);
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st.v[4] ^= aegis_aes_round(st.v[3]);
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st.v[3] ^= aegis_aes_round(st.v[2]);
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st.v[2] ^= aegis_aes_round(st.v[1]);
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st.v[1] ^= aegis_aes_round(st.v[0]);
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st.v[0] ^= m;
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return st;
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}
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static inline __attribute__((always_inline))
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void preload_sbox(void)
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{
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if (!IS_ENABLED(CONFIG_ARM64) ||
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!IS_ENABLED(CONFIG_CC_IS_GCC) ||
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__builtin_expect(aegis128_have_aes_insn, 1))
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return;
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asm("ld1 {v16.16b-v19.16b}, [%0], #64 \n\t"
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"ld1 {v20.16b-v23.16b}, [%0], #64 \n\t"
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"ld1 {v24.16b-v27.16b}, [%0], #64 \n\t"
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"ld1 {v28.16b-v31.16b}, [%0] \n\t"
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:: "r"(crypto_aes_sbox));
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}
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void crypto_aegis128_init_neon(void *state, const void *key, const void *iv)
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{
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static const uint8_t const0[] = {
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0x00, 0x01, 0x01, 0x02, 0x03, 0x05, 0x08, 0x0d,
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0x15, 0x22, 0x37, 0x59, 0x90, 0xe9, 0x79, 0x62,
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};
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static const uint8_t const1[] = {
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0xdb, 0x3d, 0x18, 0x55, 0x6d, 0xc2, 0x2f, 0xf1,
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0x20, 0x11, 0x31, 0x42, 0x73, 0xb5, 0x28, 0xdd,
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};
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uint8x16_t k = vld1q_u8(key);
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uint8x16_t kiv = k ^ vld1q_u8(iv);
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struct aegis128_state st = {{
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kiv,
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vld1q_u8(const1),
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vld1q_u8(const0),
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k ^ vld1q_u8(const0),
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k ^ vld1q_u8(const1),
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}};
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int i;
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preload_sbox();
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for (i = 0; i < 5; i++) {
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st = aegis128_update_neon(st, k);
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st = aegis128_update_neon(st, kiv);
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}
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aegis128_save_state_neon(st, state);
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}
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void crypto_aegis128_update_neon(void *state, const void *msg)
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{
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struct aegis128_state st = aegis128_load_state_neon(state);
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preload_sbox();
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st = aegis128_update_neon(st, vld1q_u8(msg));
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aegis128_save_state_neon(st, state);
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}
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#ifdef CONFIG_ARM
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/*
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* AArch32 does not provide these intrinsics natively because it does not
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* implement the underlying instructions. AArch32 only provides 64-bit
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* wide vtbl.8/vtbx.8 instruction, so use those instead.
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*/
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static uint8x16_t vqtbl1q_u8(uint8x16_t a, uint8x16_t b)
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{
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union {
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uint8x16_t val;
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uint8x8x2_t pair;
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} __a = { a };
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return vcombine_u8(vtbl2_u8(__a.pair, vget_low_u8(b)),
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vtbl2_u8(__a.pair, vget_high_u8(b)));
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}
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static uint8x16_t vqtbx1q_u8(uint8x16_t v, uint8x16_t a, uint8x16_t b)
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{
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union {
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uint8x16_t val;
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uint8x8x2_t pair;
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} __a = { a };
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return vcombine_u8(vtbx2_u8(vget_low_u8(v), __a.pair, vget_low_u8(b)),
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vtbx2_u8(vget_high_u8(v), __a.pair, vget_high_u8(b)));
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}
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static int8_t vminvq_s8(int8x16_t v)
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{
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int8x8_t s = vpmin_s8(vget_low_s8(v), vget_high_s8(v));
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s = vpmin_s8(s, s);
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s = vpmin_s8(s, s);
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s = vpmin_s8(s, s);
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return vget_lane_s8(s, 0);
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}
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#endif
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static const uint8_t permute[] __aligned(64) = {
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-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
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0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
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-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
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};
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void crypto_aegis128_encrypt_chunk_neon(void *state, void *dst, const void *src,
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unsigned int size)
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{
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struct aegis128_state st = aegis128_load_state_neon(state);
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const int short_input = size < AEGIS_BLOCK_SIZE;
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uint8x16_t msg;
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preload_sbox();
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while (size >= AEGIS_BLOCK_SIZE) {
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uint8x16_t s = st.v[1] ^ (st.v[2] & st.v[3]) ^ st.v[4];
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msg = vld1q_u8(src);
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st = aegis128_update_neon(st, msg);
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msg ^= s;
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vst1q_u8(dst, msg);
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size -= AEGIS_BLOCK_SIZE;
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src += AEGIS_BLOCK_SIZE;
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dst += AEGIS_BLOCK_SIZE;
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}
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if (size > 0) {
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uint8x16_t s = st.v[1] ^ (st.v[2] & st.v[3]) ^ st.v[4];
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uint8_t buf[AEGIS_BLOCK_SIZE];
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const void *in = src;
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void *out = dst;
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uint8x16_t m;
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if (__builtin_expect(short_input, 0))
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in = out = memcpy(buf + AEGIS_BLOCK_SIZE - size, src, size);
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m = vqtbl1q_u8(vld1q_u8(in + size - AEGIS_BLOCK_SIZE),
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vld1q_u8(permute + 32 - size));
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st = aegis128_update_neon(st, m);
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vst1q_u8(out + size - AEGIS_BLOCK_SIZE,
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vqtbl1q_u8(m ^ s, vld1q_u8(permute + size)));
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if (__builtin_expect(short_input, 0))
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memcpy(dst, out, size);
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else
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vst1q_u8(out - AEGIS_BLOCK_SIZE, msg);
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}
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aegis128_save_state_neon(st, state);
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}
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void crypto_aegis128_decrypt_chunk_neon(void *state, void *dst, const void *src,
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unsigned int size)
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{
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struct aegis128_state st = aegis128_load_state_neon(state);
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const int short_input = size < AEGIS_BLOCK_SIZE;
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uint8x16_t msg;
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preload_sbox();
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while (size >= AEGIS_BLOCK_SIZE) {
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msg = vld1q_u8(src) ^ st.v[1] ^ (st.v[2] & st.v[3]) ^ st.v[4];
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st = aegis128_update_neon(st, msg);
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vst1q_u8(dst, msg);
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size -= AEGIS_BLOCK_SIZE;
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src += AEGIS_BLOCK_SIZE;
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dst += AEGIS_BLOCK_SIZE;
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}
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if (size > 0) {
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uint8x16_t s = st.v[1] ^ (st.v[2] & st.v[3]) ^ st.v[4];
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uint8_t buf[AEGIS_BLOCK_SIZE];
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const void *in = src;
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void *out = dst;
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uint8x16_t m;
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if (__builtin_expect(short_input, 0))
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in = out = memcpy(buf + AEGIS_BLOCK_SIZE - size, src, size);
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m = s ^ vqtbx1q_u8(s, vld1q_u8(in + size - AEGIS_BLOCK_SIZE),
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vld1q_u8(permute + 32 - size));
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st = aegis128_update_neon(st, m);
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vst1q_u8(out + size - AEGIS_BLOCK_SIZE,
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vqtbl1q_u8(m, vld1q_u8(permute + size)));
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if (__builtin_expect(short_input, 0))
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memcpy(dst, out, size);
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else
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vst1q_u8(out - AEGIS_BLOCK_SIZE, msg);
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}
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aegis128_save_state_neon(st, state);
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}
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int crypto_aegis128_final_neon(void *state, void *tag_xor,
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unsigned int assoclen,
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unsigned int cryptlen,
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unsigned int authsize)
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{
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struct aegis128_state st = aegis128_load_state_neon(state);
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uint8x16_t v;
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int i;
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preload_sbox();
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v = st.v[3] ^ (uint8x16_t)vcombine_u64(vmov_n_u64(8ULL * assoclen),
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vmov_n_u64(8ULL * cryptlen));
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for (i = 0; i < 7; i++)
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st = aegis128_update_neon(st, v);
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v = st.v[0] ^ st.v[1] ^ st.v[2] ^ st.v[3] ^ st.v[4];
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if (authsize > 0) {
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v = vqtbl1q_u8(~vceqq_u8(v, vld1q_u8(tag_xor)),
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vld1q_u8(permute + authsize));
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return vminvq_s8((int8x16_t)v);
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}
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vst1q_u8(tag_xor, v);
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return 0;
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}
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