148 lines
3.8 KiB
C
148 lines
3.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Tegra host1x Interrupt Management
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*
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* Copyright (C) 2010 Google, Inc.
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* Copyright (c) 2010-2013, NVIDIA Corporation.
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*/
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include "../intr.h"
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#include "../dev.h"
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struct host1x_intr_irq_data {
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struct host1x *host;
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u32 offset;
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};
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static irqreturn_t syncpt_thresh_isr(int irq, void *dev_id)
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{
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struct host1x_intr_irq_data *irq_data = dev_id;
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struct host1x *host = irq_data->host;
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unsigned long reg;
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unsigned int i, id;
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for (i = irq_data->offset; i < DIV_ROUND_UP(host->info->nb_pts, 32);
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i += host->num_syncpt_irqs) {
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reg = host1x_sync_readl(host,
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HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(i));
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host1x_sync_writel(host, reg,
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HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(i));
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host1x_sync_writel(host, reg,
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HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(i));
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for_each_set_bit(id, ®, 32)
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host1x_intr_handle_interrupt(host, i * 32 + id);
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}
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return IRQ_HANDLED;
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}
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static void host1x_intr_disable_all_syncpt_intrs(struct host1x *host)
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{
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unsigned int i;
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for (i = 0; i < DIV_ROUND_UP(host->info->nb_pts, 32); ++i) {
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host1x_sync_writel(host, 0xffffffffu,
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HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(i));
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host1x_sync_writel(host, 0xffffffffu,
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HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(i));
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}
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}
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static void intr_hw_init(struct host1x *host, u32 cpm)
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{
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#if HOST1X_HW < 6
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/* disable the ip_busy_timeout. this prevents write drops */
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host1x_sync_writel(host, 0, HOST1X_SYNC_IP_BUSY_TIMEOUT);
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/*
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* increase the auto-ack timout to the maximum value. 2d will hang
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* otherwise on Tegra2.
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*/
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host1x_sync_writel(host, 0xff, HOST1X_SYNC_CTXSW_TIMEOUT_CFG);
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/* update host clocks per usec */
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host1x_sync_writel(host, cpm, HOST1X_SYNC_USEC_CLK);
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#endif
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#if HOST1X_HW >= 8
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u32 id;
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/*
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* Program threshold interrupt destination among 8 lines per VM,
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* per syncpoint. For each group of 32 syncpoints (corresponding to one
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* interrupt status register), direct to one interrupt line, going
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* around in a round robin fashion.
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*/
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for (id = 0; id < host->info->nb_pts; id++) {
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u32 reg_offset = id / 32;
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u32 irq_index = reg_offset % host->num_syncpt_irqs;
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host1x_sync_writel(host, irq_index, HOST1X_SYNC_SYNCPT_INTR_DEST(id));
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}
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#endif
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}
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static int
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host1x_intr_init_host_sync(struct host1x *host, u32 cpm)
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{
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int err, i;
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struct host1x_intr_irq_data *irq_data;
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irq_data = devm_kcalloc(host->dev, host->num_syncpt_irqs, sizeof(irq_data[0]), GFP_KERNEL);
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if (!irq_data)
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return -ENOMEM;
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host1x_hw_intr_disable_all_syncpt_intrs(host);
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for (i = 0; i < host->num_syncpt_irqs; i++) {
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irq_data[i].host = host;
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irq_data[i].offset = i;
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err = devm_request_irq(host->dev, host->syncpt_irqs[i],
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syncpt_thresh_isr, IRQF_SHARED,
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"host1x_syncpt", &irq_data[i]);
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if (err < 0)
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return err;
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}
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intr_hw_init(host, cpm);
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return 0;
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}
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static void host1x_intr_set_syncpt_threshold(struct host1x *host,
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unsigned int id,
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u32 thresh)
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{
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host1x_sync_writel(host, thresh, HOST1X_SYNC_SYNCPT_INT_THRESH(id));
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}
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static void host1x_intr_enable_syncpt_intr(struct host1x *host,
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unsigned int id)
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{
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host1x_sync_writel(host, BIT(id % 32),
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HOST1X_SYNC_SYNCPT_THRESH_INT_ENABLE_CPU0(id / 32));
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}
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static void host1x_intr_disable_syncpt_intr(struct host1x *host,
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unsigned int id)
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{
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host1x_sync_writel(host, BIT(id % 32),
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HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(id / 32));
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host1x_sync_writel(host, BIT(id % 32),
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HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(id / 32));
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}
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static const struct host1x_intr_ops host1x_intr_ops = {
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.init_host_sync = host1x_intr_init_host_sync,
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.set_syncpt_threshold = host1x_intr_set_syncpt_threshold,
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.enable_syncpt_intr = host1x_intr_enable_syncpt_intr,
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.disable_syncpt_intr = host1x_intr_disable_syncpt_intr,
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.disable_all_syncpt_intrs = host1x_intr_disable_all_syncpt_intrs,
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};
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