168 lines
3.4 KiB
C
168 lines
3.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
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/*
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* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
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* Author(s): Gabriel Fernandez <gabriel.fernandez@foss.st.com>
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*/
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#ifndef _DT_BINDINGS_STM32MP25_RESET_H_
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#define _DT_BINDINGS_STM32MP25_RESET_H_
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#define TIM1_R 0
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#define TIM2_R 1
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#define TIM3_R 2
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#define TIM4_R 3
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#define TIM5_R 4
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#define TIM6_R 5
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#define TIM7_R 6
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#define TIM8_R 7
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#define TIM10_R 8
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#define TIM11_R 9
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#define TIM12_R 10
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#define TIM13_R 11
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#define TIM14_R 12
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#define TIM15_R 13
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#define TIM16_R 14
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#define TIM17_R 15
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#define TIM20_R 16
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#define LPTIM1_R 17
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#define LPTIM2_R 18
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#define LPTIM3_R 19
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#define LPTIM4_R 20
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#define LPTIM5_R 21
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#define SPI1_R 22
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#define SPI2_R 23
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#define SPI3_R 24
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#define SPI4_R 25
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#define SPI5_R 26
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#define SPI6_R 27
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#define SPI7_R 28
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#define SPI8_R 29
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#define SPDIFRX_R 30
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#define USART1_R 31
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#define USART2_R 32
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#define USART3_R 33
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#define UART4_R 34
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#define UART5_R 35
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#define USART6_R 36
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#define UART7_R 37
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#define UART8_R 38
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#define UART9_R 39
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#define LPUART1_R 40
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#define IS2M_R 41
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#define I2C1_R 42
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#define I2C2_R 43
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#define I2C3_R 44
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#define I2C4_R 45
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#define I2C5_R 46
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#define I2C6_R 47
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#define I2C7_R 48
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#define I2C8_R 49
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#define SAI1_R 50
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#define SAI2_R 51
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#define SAI3_R 52
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#define SAI4_R 53
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#define MDF1_R 54
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#define MDF2_R 55
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#define FDCAN_R 56
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#define HDP_R 57
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#define ADC12_R 58
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#define ADC3_R 59
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#define ETH1_R 60
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#define ETH2_R 61
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#define USBH_R 62
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#define USB2PHY1_R 63
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#define USB2PHY2_R 64
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#define USB3DR_R 65
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#define USB3PCIEPHY_R 66
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#define USBTC_R 67
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#define ETHSW_R 68
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#define SDMMC1_R 69
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#define SDMMC1DLL_R 70
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#define SDMMC2_R 71
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#define SDMMC2DLL_R 72
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#define SDMMC3_R 73
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#define SDMMC3DLL_R 74
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#define GPU_R 75
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#define LTDC_R 76
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#define DSI_R 77
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#define LVDS_R 78
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#define CSI_R 79
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#define DCMIPP_R 80
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#define CCI_R 81
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#define VDEC_R 82
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#define VENC_R 83
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#define WWDG1_R 84
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#define WWDG2_R 85
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#define VREF_R 86
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#define DTS_R 87
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#define CRC_R 88
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#define SERC_R 89
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#define OSPIIOM_R 90
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#define I3C1_R 91
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#define I3C2_R 92
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#define I3C3_R 93
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#define I3C4_R 94
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#define IWDG2_KER_R 95
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#define IWDG4_KER_R 96
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#define RNG_R 97
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#define PKA_R 98
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#define SAES_R 99
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#define HASH_R 100
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#define CRYP1_R 101
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#define CRYP2_R 102
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#define PCIE_R 103
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#define OSPI1_R 104
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#define OSPI1DLL_R 105
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#define OSPI2_R 106
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#define OSPI2DLL_R 107
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#define FMC_R 108
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#define DBG_R 109
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#define GPIOA_R 110
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#define GPIOB_R 111
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#define GPIOC_R 112
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#define GPIOD_R 113
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#define GPIOE_R 114
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#define GPIOF_R 115
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#define GPIOG_R 116
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#define GPIOH_R 117
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#define GPIOI_R 118
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#define GPIOJ_R 119
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#define GPIOK_R 120
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#define GPIOZ_R 121
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#define HPDMA1_R 122
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#define HPDMA2_R 123
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#define HPDMA3_R 124
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#define LPDMA_R 125
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#define HSEM_R 126
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#define IPCC1_R 127
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#define IPCC2_R 128
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#define C2_HOLDBOOT_R 129
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#define C1_HOLDBOOT_R 130
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#define C1_R 131
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#define C1P1POR_R 132
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#define C1P1_R 133
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#define C2_R 134
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#define C3_R 135
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#define SYS_R 136
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#define VSW_R 137
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#define C1MS_R 138
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#define DDRCP_R 139
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#define DDRCAPB_R 140
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#define DDRPHYCAPB_R 141
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#define DDRCFG_R 142
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#define DDR_R 143
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#define STM32MP25_LAST_RESET 144
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#define RST_SCMI_C1_R 0
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#define RST_SCMI_C2_R 1
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#define RST_SCMI_C1_HOLDBOOT_R 2
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#define RST_SCMI_C2_HOLDBOOT_R 3
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#define RST_SCMI_FMC 4
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#define RST_SCMI_OSPI1 5
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#define RST_SCMI_OSPI1DLL 6
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#define RST_SCMI_OSPI2 7
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#define RST_SCMI_OSPI2DLL 8
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#endif /* _DT_BINDINGS_STM32MP25_RESET_H_ */
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