166 lines
3.6 KiB
C
166 lines
3.6 KiB
C
/*
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* numaq_32.c - Low-level PCI access for NUMA-Q machines
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*/
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/nodemask.h>
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#include <asm/apic.h>
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#include <asm/mpspec.h>
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#include <asm/pci_x86.h>
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#include <asm/numaq.h>
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#define BUS2QUAD(global) (mp_bus_id_to_node[global])
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#define BUS2LOCAL(global) (mp_bus_id_to_local[global])
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#define QUADLOCAL2BUS(quad,local) (quad_local_to_mp_bus_id[quad][local])
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#define PCI_CONF1_MQ_ADDRESS(bus, devfn, reg) \
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(0x80000000 | (BUS2LOCAL(bus) << 16) | (devfn << 8) | (reg & ~3))
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static void write_cf8(unsigned bus, unsigned devfn, unsigned reg)
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{
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unsigned val = PCI_CONF1_MQ_ADDRESS(bus, devfn, reg);
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if (xquad_portio)
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writel(val, XQUAD_PORT_ADDR(0xcf8, BUS2QUAD(bus)));
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else
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outl(val, 0xCF8);
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}
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static int pci_conf1_mq_read(unsigned int seg, unsigned int bus,
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unsigned int devfn, int reg, int len, u32 *value)
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{
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unsigned long flags;
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void *adr __iomem = XQUAD_PORT_ADDR(0xcfc, BUS2QUAD(bus));
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WARN_ON(seg);
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if (!value || (bus >= MAX_MP_BUSSES) || (devfn > 255) || (reg > 255))
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return -EINVAL;
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raw_spin_lock_irqsave(&pci_config_lock, flags);
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write_cf8(bus, devfn, reg);
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switch (len) {
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case 1:
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if (xquad_portio)
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*value = readb(adr + (reg & 3));
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else
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*value = inb(0xCFC + (reg & 3));
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break;
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case 2:
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if (xquad_portio)
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*value = readw(adr + (reg & 2));
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else
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*value = inw(0xCFC + (reg & 2));
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break;
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case 4:
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if (xquad_portio)
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*value = readl(adr);
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else
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*value = inl(0xCFC);
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break;
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}
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raw_spin_unlock_irqrestore(&pci_config_lock, flags);
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return 0;
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}
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static int pci_conf1_mq_write(unsigned int seg, unsigned int bus,
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unsigned int devfn, int reg, int len, u32 value)
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{
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unsigned long flags;
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void *adr __iomem = XQUAD_PORT_ADDR(0xcfc, BUS2QUAD(bus));
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WARN_ON(seg);
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if ((bus >= MAX_MP_BUSSES) || (devfn > 255) || (reg > 255))
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return -EINVAL;
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raw_spin_lock_irqsave(&pci_config_lock, flags);
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write_cf8(bus, devfn, reg);
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switch (len) {
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case 1:
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if (xquad_portio)
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writeb(value, adr + (reg & 3));
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else
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outb((u8)value, 0xCFC + (reg & 3));
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break;
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case 2:
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if (xquad_portio)
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writew(value, adr + (reg & 2));
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else
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outw((u16)value, 0xCFC + (reg & 2));
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break;
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case 4:
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if (xquad_portio)
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writel(value, adr + reg);
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else
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outl((u32)value, 0xCFC);
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break;
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}
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raw_spin_unlock_irqrestore(&pci_config_lock, flags);
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return 0;
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}
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#undef PCI_CONF1_MQ_ADDRESS
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static const struct pci_raw_ops pci_direct_conf1_mq = {
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.read = pci_conf1_mq_read,
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.write = pci_conf1_mq_write
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};
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static void pci_fixup_i450nx(struct pci_dev *d)
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{
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/*
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* i450NX -- Find and scan all secondary buses on all PXB's.
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*/
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int pxb, reg;
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u8 busno, suba, subb;
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int quad = BUS2QUAD(d->bus->number);
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dev_info(&d->dev, "searching for i450NX host bridges\n");
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reg = 0xd0;
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for(pxb=0; pxb<2; pxb++) {
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pci_read_config_byte(d, reg++, &busno);
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pci_read_config_byte(d, reg++, &suba);
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pci_read_config_byte(d, reg++, &subb);
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dev_dbg(&d->dev, "i450NX PXB %d: %02x/%02x/%02x\n",
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pxb, busno, suba, subb);
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if (busno) {
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/* Bus A */
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pci_scan_bus_with_sysdata(QUADLOCAL2BUS(quad, busno));
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}
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if (suba < subb) {
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/* Bus B */
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pci_scan_bus_with_sysdata(QUADLOCAL2BUS(quad, suba+1));
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}
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}
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pcibios_last_bus = -1;
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, pci_fixup_i450nx);
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int __init pci_numaq_init(void)
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{
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int quad;
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raw_pci_ops = &pci_direct_conf1_mq;
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pci_root_bus = pcibios_scan_root(0);
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if (num_online_nodes() > 1)
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for_each_online_node(quad) {
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if (quad == 0)
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continue;
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printk("Scanning PCI bus %d for quad %d\n",
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QUADLOCAL2BUS(quad,0), quad);
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pci_scan_bus_with_sysdata(QUADLOCAL2BUS(quad, 0));
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}
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return 0;
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}
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