282 lines
9.6 KiB
C
282 lines
9.6 KiB
C
#ifndef __ddr2_defs_h
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#define __ddr2_defs_h
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/*
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* This file is autogenerated from
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* file: ddr2.r
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*
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* by ../../../tools/rdesc/bin/rdes2c -outfile ddr2_defs.h ddr2.r
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* Any changes here will be lost.
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*
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* -*- buffer-read-only: t -*-
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*/
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/* Main access macros */
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#ifndef REG_RD
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#define REG_RD( scope, inst, reg ) \
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REG_READ( reg_##scope##_##reg, \
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(inst) + REG_RD_ADDR_##scope##_##reg )
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#endif
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#ifndef REG_WR
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#define REG_WR( scope, inst, reg, val ) \
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REG_WRITE( reg_##scope##_##reg, \
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(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
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#endif
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#ifndef REG_RD_VECT
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#define REG_RD_VECT( scope, inst, reg, index ) \
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REG_READ( reg_##scope##_##reg, \
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(inst) + REG_RD_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg )
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#endif
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#ifndef REG_WR_VECT
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#define REG_WR_VECT( scope, inst, reg, index, val ) \
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REG_WRITE( reg_##scope##_##reg, \
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(inst) + REG_WR_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg, (val) )
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#endif
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#ifndef REG_RD_INT
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#define REG_RD_INT( scope, inst, reg ) \
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REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
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#endif
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#ifndef REG_WR_INT
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#define REG_WR_INT( scope, inst, reg, val ) \
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REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
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#endif
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#ifndef REG_RD_INT_VECT
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#define REG_RD_INT_VECT( scope, inst, reg, index ) \
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REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg )
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#endif
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#ifndef REG_WR_INT_VECT
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#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
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REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg, (val) )
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#endif
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#ifndef REG_TYPE_CONV
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#define REG_TYPE_CONV( type, orgtype, val ) \
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( { union { orgtype o; type n; } r; r.o = val; r.n; } )
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#endif
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#ifndef reg_page_size
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#define reg_page_size 8192
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#endif
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#ifndef REG_ADDR
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#define REG_ADDR( scope, inst, reg ) \
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( (inst) + REG_RD_ADDR_##scope##_##reg )
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#endif
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#ifndef REG_ADDR_VECT
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#define REG_ADDR_VECT( scope, inst, reg, index ) \
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( (inst) + REG_RD_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg )
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#endif
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/* C-code for register scope ddr2 */
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/* Register rw_cfg, scope ddr2, type rw */
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typedef struct {
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unsigned int col_width : 4;
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unsigned int nr_banks : 1;
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unsigned int bw : 1;
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unsigned int nr_ref : 4;
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unsigned int ref_interval : 11;
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unsigned int odt_ctrl : 2;
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unsigned int odt_mem : 1;
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unsigned int imp_strength : 1;
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unsigned int auto_imp_cal : 1;
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unsigned int imp_cal_override : 1;
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unsigned int dll_override : 1;
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unsigned int dummy1 : 4;
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} reg_ddr2_rw_cfg;
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#define REG_RD_ADDR_ddr2_rw_cfg 0
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#define REG_WR_ADDR_ddr2_rw_cfg 0
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/* Register rw_timing, scope ddr2, type rw */
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typedef struct {
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unsigned int wr : 3;
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unsigned int rcd : 3;
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unsigned int rp : 3;
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unsigned int ras : 4;
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unsigned int rfc : 7;
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unsigned int rc : 5;
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unsigned int rtp : 2;
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unsigned int rtw : 3;
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unsigned int wtr : 2;
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} reg_ddr2_rw_timing;
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#define REG_RD_ADDR_ddr2_rw_timing 4
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#define REG_WR_ADDR_ddr2_rw_timing 4
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/* Register rw_latency, scope ddr2, type rw */
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typedef struct {
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unsigned int cas : 3;
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unsigned int additive : 3;
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unsigned int dummy1 : 26;
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} reg_ddr2_rw_latency;
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#define REG_RD_ADDR_ddr2_rw_latency 8
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#define REG_WR_ADDR_ddr2_rw_latency 8
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/* Register rw_phy_cfg, scope ddr2, type rw */
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typedef struct {
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unsigned int en : 1;
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unsigned int dummy1 : 31;
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} reg_ddr2_rw_phy_cfg;
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#define REG_RD_ADDR_ddr2_rw_phy_cfg 12
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#define REG_WR_ADDR_ddr2_rw_phy_cfg 12
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/* Register rw_phy_ctrl, scope ddr2, type rw */
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typedef struct {
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unsigned int rst : 1;
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unsigned int cal_rst : 1;
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unsigned int cal_start : 1;
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unsigned int dummy1 : 29;
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} reg_ddr2_rw_phy_ctrl;
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#define REG_RD_ADDR_ddr2_rw_phy_ctrl 16
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#define REG_WR_ADDR_ddr2_rw_phy_ctrl 16
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/* Register rw_ctrl, scope ddr2, type rw */
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typedef struct {
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unsigned int mrs_data : 16;
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unsigned int cmd : 8;
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unsigned int dummy1 : 8;
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} reg_ddr2_rw_ctrl;
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#define REG_RD_ADDR_ddr2_rw_ctrl 20
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#define REG_WR_ADDR_ddr2_rw_ctrl 20
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/* Register rw_pwr_down, scope ddr2, type rw */
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typedef struct {
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unsigned int self_ref : 2;
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unsigned int phy_en : 1;
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unsigned int dummy1 : 29;
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} reg_ddr2_rw_pwr_down;
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#define REG_RD_ADDR_ddr2_rw_pwr_down 24
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#define REG_WR_ADDR_ddr2_rw_pwr_down 24
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/* Register r_stat, scope ddr2, type r */
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typedef struct {
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unsigned int dll_lock : 1;
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unsigned int dll_delay_code : 7;
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unsigned int imp_cal_done : 1;
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unsigned int imp_cal_fault : 1;
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unsigned int cal_imp_pu : 4;
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unsigned int cal_imp_pd : 4;
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unsigned int dummy1 : 14;
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} reg_ddr2_r_stat;
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#define REG_RD_ADDR_ddr2_r_stat 28
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/* Register rw_imp_ctrl, scope ddr2, type rw */
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typedef struct {
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unsigned int imp_pu : 4;
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unsigned int imp_pd : 4;
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unsigned int dummy1 : 24;
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} reg_ddr2_rw_imp_ctrl;
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#define REG_RD_ADDR_ddr2_rw_imp_ctrl 32
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#define REG_WR_ADDR_ddr2_rw_imp_ctrl 32
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#define STRIDE_ddr2_rw_dll_ctrl 4
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/* Register rw_dll_ctrl, scope ddr2, type rw */
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typedef struct {
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unsigned int mode : 1;
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unsigned int clk_delay : 7;
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unsigned int dummy1 : 24;
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} reg_ddr2_rw_dll_ctrl;
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#define REG_RD_ADDR_ddr2_rw_dll_ctrl 36
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#define REG_WR_ADDR_ddr2_rw_dll_ctrl 36
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#define STRIDE_ddr2_rw_dqs_dll_ctrl 4
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/* Register rw_dqs_dll_ctrl, scope ddr2, type rw */
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typedef struct {
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unsigned int dqs90_delay : 7;
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unsigned int dqs180_delay : 7;
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unsigned int dqs270_delay : 7;
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unsigned int dqs360_delay : 7;
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unsigned int dummy1 : 4;
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} reg_ddr2_rw_dqs_dll_ctrl;
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#define REG_RD_ADDR_ddr2_rw_dqs_dll_ctrl 52
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#define REG_WR_ADDR_ddr2_rw_dqs_dll_ctrl 52
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/* Constants */
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enum {
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regk_ddr2_al0 = 0x00000000,
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regk_ddr2_al1 = 0x00000008,
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regk_ddr2_al2 = 0x00000010,
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regk_ddr2_al3 = 0x00000018,
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regk_ddr2_al4 = 0x00000020,
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regk_ddr2_auto = 0x00000003,
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regk_ddr2_bank4 = 0x00000000,
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regk_ddr2_bank8 = 0x00000001,
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regk_ddr2_bl4 = 0x00000002,
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regk_ddr2_bl8 = 0x00000003,
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regk_ddr2_bt_il = 0x00000008,
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regk_ddr2_bt_seq = 0x00000000,
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regk_ddr2_bw16 = 0x00000001,
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regk_ddr2_bw32 = 0x00000000,
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regk_ddr2_cas2 = 0x00000020,
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regk_ddr2_cas3 = 0x00000030,
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regk_ddr2_cas4 = 0x00000040,
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regk_ddr2_cas5 = 0x00000050,
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regk_ddr2_deselect = 0x000000c0,
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regk_ddr2_dic_weak = 0x00000002,
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regk_ddr2_direct = 0x00000001,
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regk_ddr2_dis = 0x00000000,
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regk_ddr2_dll_dis = 0x00000001,
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regk_ddr2_dll_en = 0x00000000,
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regk_ddr2_dll_rst = 0x00000100,
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regk_ddr2_emrs = 0x00000081,
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regk_ddr2_emrs2 = 0x00000082,
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regk_ddr2_emrs3 = 0x00000083,
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regk_ddr2_full = 0x00000001,
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regk_ddr2_hi_ref_rate = 0x00000080,
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regk_ddr2_mrs = 0x00000080,
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regk_ddr2_no = 0x00000000,
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regk_ddr2_nop = 0x000000b8,
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regk_ddr2_ocd_adj = 0x00000200,
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regk_ddr2_ocd_default = 0x00000380,
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regk_ddr2_ocd_drive0 = 0x00000100,
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regk_ddr2_ocd_drive1 = 0x00000080,
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regk_ddr2_ocd_exit = 0x00000000,
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regk_ddr2_odt_dis = 0x00000000,
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regk_ddr2_offs = 0x00000000,
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regk_ddr2_pre = 0x00000090,
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regk_ddr2_pre_all = 0x00000400,
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regk_ddr2_pwr_down_fast = 0x00000000,
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regk_ddr2_pwr_down_slow = 0x00001000,
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regk_ddr2_ref = 0x00000088,
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regk_ddr2_rtt150 = 0x00000040,
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regk_ddr2_rtt50 = 0x00000044,
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regk_ddr2_rtt75 = 0x00000004,
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regk_ddr2_rw_cfg_default = 0x00186000,
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regk_ddr2_rw_dll_ctrl_default = 0x00000000,
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regk_ddr2_rw_dll_ctrl_size = 0x00000004,
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regk_ddr2_rw_dqs_dll_ctrl_default = 0x00000000,
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regk_ddr2_rw_dqs_dll_ctrl_size = 0x00000004,
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regk_ddr2_rw_latency_default = 0x00000000,
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regk_ddr2_rw_phy_cfg_default = 0x00000000,
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regk_ddr2_rw_pwr_down_default = 0x00000000,
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regk_ddr2_rw_timing_default = 0x00000000,
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regk_ddr2_s1Gb = 0x0000001a,
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regk_ddr2_s256Mb = 0x0000000f,
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regk_ddr2_s2Gb = 0x00000027,
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regk_ddr2_s4Gb = 0x00000042,
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regk_ddr2_s512Mb = 0x00000015,
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regk_ddr2_temp0_85 = 0x00000618,
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regk_ddr2_temp85_95 = 0x0000030c,
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regk_ddr2_term150 = 0x00000002,
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regk_ddr2_term50 = 0x00000003,
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regk_ddr2_term75 = 0x00000001,
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regk_ddr2_test = 0x00000080,
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regk_ddr2_weak = 0x00000000,
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regk_ddr2_wr2 = 0x00000200,
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regk_ddr2_wr3 = 0x00000400,
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regk_ddr2_yes = 0x00000001
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};
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#endif /* __ddr2_defs_h */
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