original_kernel/arch/arm/mm
Catalin Marinas 141fa40cff [ARM] 3356/1: Workaround for the ARM1136 I-cache invalidation problem
Patch from Catalin Marinas

ARM1136 erratum 371025 (category 2) specifies that, under rare
conditions, an invalidate I-cache by MVA (line or range) operation can
fail to invalidate a cache line. The recommended workaround is to
either invalidate the entire I-cache or invalidate the range by
set/way rather than MVA.

Note that for a 16K cache size, invalidating a 4K page by set/way is
equivalent to invalidating the entire I-cache.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-03-10 22:26:47 +00:00
..
Kconfig
Makefile
abort-ev4.S
abort-ev4t.S
abort-ev5t.S
abort-ev5tj.S
abort-ev6.S
abort-lv4t.S
abort-macro.S
alignment.c
cache-v3.S
cache-v4.S
cache-v4wb.S
cache-v4wt.S
cache-v6.S [ARM] 3356/1: Workaround for the ARM1136 I-cache invalidation problem 2006-03-10 22:26:47 +00:00
consistent.c
copypage-v3.S
copypage-v4mc.c
copypage-v4wb.S
copypage-v4wt.S
copypage-v6.c
copypage-xscale.c
discontig.c
extable.c
fault-armv.c
fault.c
fault.h
flush.c [ARM] 3356/1: Workaround for the ARM1136 I-cache invalidation problem 2006-03-10 22:26:47 +00:00
init.c
ioremap.c
mm-armv.c
mmap.c
mmu.c
proc-arm6_7.S
proc-arm720.S
proc-arm920.S
proc-arm922.S
proc-arm925.S
proc-arm926.S
proc-arm1020.S
proc-arm1020e.S
proc-arm1022.S
proc-arm1026.S
proc-macros.S
proc-sa110.S
proc-sa1100.S
proc-syms.c
proc-v6.S
proc-xscale.S
tlb-v3.S
tlb-v4.S
tlb-v4wb.S
tlb-v4wbi.S
tlb-v6.S