127 lines
3.0 KiB
C
127 lines
3.0 KiB
C
/*
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* linux/arch/arm/mach-omap2/timer-gp.c
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*
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* OMAP2 GP timer support.
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*
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* Copyright (C) 2005 Nokia Corporation
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* Author: Paul Mundt <paul.mundt@nokia.com>
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* Juha Yrjölä <juha.yrjola@nokia.com>
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*
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* Some parts based off of TI's 24xx code:
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*
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* Copyright (C) 2004 Texas Instruments, Inc.
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*
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* Roughly modelled after the OMAP1 MPU timer code.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/time.h>
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#include <linux/interrupt.h>
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#include <linux/err.h>
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#include <asm/mach/time.h>
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#include <asm/delay.h>
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#include <asm/io.h>
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#include <asm/hardware/clock.h>
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#define OMAP2_GP_TIMER1_BASE 0x48028000
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#define OMAP2_GP_TIMER2_BASE 0x4802a000
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#define OMAP2_GP_TIMER3_BASE 0x48078000
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#define OMAP2_GP_TIMER4_BASE 0x4807a000
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#define GP_TIMER_TIDR 0x00
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#define GP_TIMER_TISR 0x18
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#define GP_TIMER_TIER 0x1c
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#define GP_TIMER_TCLR 0x24
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#define GP_TIMER_TCRR 0x28
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#define GP_TIMER_TLDR 0x2c
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#define GP_TIMER_TSICR 0x40
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#define OS_TIMER_NR 1 /* GP timer 2 */
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static unsigned long timer_base[] = {
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IO_ADDRESS(OMAP2_GP_TIMER1_BASE),
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IO_ADDRESS(OMAP2_GP_TIMER2_BASE),
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IO_ADDRESS(OMAP2_GP_TIMER3_BASE),
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IO_ADDRESS(OMAP2_GP_TIMER4_BASE),
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};
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static inline unsigned int timer_read_reg(int nr, unsigned int reg)
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{
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return __raw_readl(timer_base[nr] + reg);
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}
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static inline void timer_write_reg(int nr, unsigned int reg, unsigned int val)
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{
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__raw_writel(val, timer_base[nr] + reg);
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}
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/* Note that we always enable the clock prescale divider bit */
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static inline void omap2_gp_timer_start(int nr, unsigned long load_val)
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{
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unsigned int tmp;
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tmp = 0xffffffff - load_val;
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timer_write_reg(nr, GP_TIMER_TLDR, tmp);
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timer_write_reg(nr, GP_TIMER_TCRR, tmp);
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timer_write_reg(nr, GP_TIMER_TIER, 1 << 1);
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timer_write_reg(nr, GP_TIMER_TCLR, (1 << 5) | (1 << 1) | 1);
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}
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static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id,
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struct pt_regs *regs)
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{
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write_seqlock(&xtime_lock);
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timer_write_reg(OS_TIMER_NR, GP_TIMER_TISR, 1 << 1);
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timer_tick(regs);
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write_sequnlock(&xtime_lock);
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return IRQ_HANDLED;
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}
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static struct irqaction omap2_gp_timer_irq = {
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.name = "gp timer",
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.flags = SA_INTERRUPT,
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.handler = omap2_gp_timer_interrupt,
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};
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static void __init omap2_gp_timer_init(void)
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{
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struct clk * sys_ck;
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u32 tick_period = 120000;
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u32 l;
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/* Reset clock and prescale value */
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timer_write_reg(OS_TIMER_NR, GP_TIMER_TCLR, 0);
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sys_ck = clk_get(NULL, "sys_ck");
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if (IS_ERR(sys_ck))
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printk(KERN_ERR "Could not get sys_ck\n");
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else {
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clk_use(sys_ck);
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tick_period = clk_get_rate(sys_ck) / 100;
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clk_put(sys_ck);
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}
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tick_period /= 2; /* Minimum prescale divider is 2 */
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tick_period -= 1;
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l = timer_read_reg(OS_TIMER_NR, GP_TIMER_TIDR);
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printk(KERN_INFO "OMAP2 GP timer (HW version %d.%d)\n",
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(l >> 4) & 0x0f, l & 0x0f);
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setup_irq(38, &omap2_gp_timer_irq);
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omap2_gp_timer_start(OS_TIMER_NR, tick_period);
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}
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struct sys_timer omap_timer = {
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.init = omap2_gp_timer_init,
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};
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