275 lines
8.7 KiB
C
275 lines
8.7 KiB
C
/*-*- linux-c -*-
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* linux/drivers/video/i810_regs.h -- Intel 810/815 Register List
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*
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* Copyright (C) 2001 Antonino Daplas<adaplas@pol.net>
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* All Rights Reserved
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*
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive for
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* more details.
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*/
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/*
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* Intel 810 Chipset Family PRM 15 3.1
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* GC Register Memory Address Map
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*
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* Based on:
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* Intel (R) 810 Chipset Family
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* Programmer s Reference Manual
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* November 1999
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* Revision 1.0
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* Order Number: 298026-001 R
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*
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* All GC registers are memory-mapped. In addition, the VGA and extended VGA registers
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* are I/O mapped.
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*/
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#ifndef __I810_REGS_H__
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#define __I810_REGS_H__
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/* Instruction and Interrupt Control Registers (01000h 02FFFh) */
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#define FENCE 0x02000
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#define PGTBL_CTL 0x02020
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#define PGTBL_ER 0x02024
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#define LRING 0x02030
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#define IRING 0x02040
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#define HWS_PGA 0x02080
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#define IPEIR 0x02088
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#define IPEHR 0x0208C
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#define INSTDONE 0x02090
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#define NOPID 0x02094
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#define HWSTAM 0x02098
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#define IER 0x020A0
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#define IIR 0x020A4
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#define IMR 0x020A8
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#define ISR 0x020AC
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#define EIR 0x020B0
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#define EMR 0x020B4
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#define ESR 0x020B8
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#define INSTPM 0x020C0
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#define INSTPS 0x020C4
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#define BBP_PTR 0x020C8
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#define ABB_SRT 0x020CC
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#define ABB_END 0x020D0
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#define DMA_FADD 0x020D4
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#define FW_BLC 0x020D8
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#define MEM_MODE 0x020DC
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/* Memory Control Registers (03000h 03FFFh) */
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#define DRT 0x03000
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#define DRAMCL 0x03001
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#define DRAMCH 0x03002
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/* Span Cursor Registers (04000h 04FFFh) */
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#define UI_SC_CTL 0x04008
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/* I/O Control Registers (05000h 05FFFh) */
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#define HVSYNC 0x05000
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#define GPIOA 0x05010
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#define GPIOB 0x05014
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/* Clock Control and Power Management Registers (06000h 06FFFh) */
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#define DCLK_0D 0x06000
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#define DCLK_1D 0x06004
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#define DCLK_2D 0x06008
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#define LCD_CLKD 0x0600C
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#define DCLK_0DS 0x06010
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#define PWR_CLKC 0x06014
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/* Graphics Translation Table Range Definition (10000h 1FFFFh) */
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#define GTT 0x10000
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/* Overlay Registers (30000h 03FFFFh) */
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#define OVOADDR 0x30000
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#define DOVOSTA 0x30008
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#define GAMMA 0x30010
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#define OBUF_0Y 0x30100
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#define OBUF_1Y 0x30104
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#define OBUF_0U 0x30108
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#define OBUF_0V 0x3010C
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#define OBUF_1U 0x30110
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#define OBUF_1V 0x30114
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#define OVOSTRIDE 0x30118
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#define YRGB_VPH 0x3011C
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#define UV_VPH 0x30120
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#define HORZ_PH 0x30124
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#define INIT_PH 0x30128
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#define DWINPOS 0x3012C
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#define DWINSZ 0x30130
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#define SWID 0x30134
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#define SWIDQW 0x30138
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#define SHEIGHT 0x3013F
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#define YRGBSCALE 0x30140
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#define UVSCALE 0x30144
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#define OVOCLRCO 0x30148
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#define OVOCLRC1 0x3014C
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#define DCLRKV 0x30150
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#define DLCRKM 0x30154
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#define SCLRKVH 0x30158
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#define SCLRKVL 0x3015C
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#define SCLRKM 0x30160
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#define OVOCONF 0x30164
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#define OVOCMD 0x30168
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#define AWINPOS 0x30170
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#define AWINZ 0x30174
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/* BLT Engine Status (40000h 4FFFFh) (Software Debug) */
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#define BR00 0x40000
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#define BRO1 0x40004
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#define BR02 0x40008
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#define BR03 0x4000C
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#define BR04 0x40010
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#define BR05 0x40014
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#define BR06 0x40018
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#define BR07 0x4001C
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#define BR08 0x40020
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#define BR09 0x40024
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#define BR10 0x40028
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#define BR11 0x4002C
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#define BR12 0x40030
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#define BR13 0x40034
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#define BR14 0x40038
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#define BR15 0x4003C
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#define BR16 0x40040
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#define BR17 0x40044
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#define BR18 0x40048
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#define BR19 0x4004C
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#define SSLADD 0x40074
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#define DSLH 0x40078
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#define DSLRADD 0x4007C
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/* LCD/TV-Out and HW DVD Registers (60000h 6FFFFh) */
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/* LCD/TV-Out */
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#define HTOTAL 0x60000
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#define HBLANK 0x60004
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#define HSYNC 0x60008
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#define VTOTAL 0x6000C
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#define VBLANK 0x60010
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#define VSYNC 0x60014
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#define LCDTV_C 0x60018
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#define OVRACT 0x6001C
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#define BCLRPAT 0x60020
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/* Display and Cursor Control Registers (70000h 7FFFFh) */
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#define DISP_SL 0x70000
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#define DISP_SLC 0x70004
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#define PIXCONF 0x70008
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#define PIXCONF1 0x70009
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#define BLTCNTL 0x7000C
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#define SWF 0x70014
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#define DPLYBASE 0x70020
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#define DPLYSTAS 0x70024
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#define CURCNTR 0x70080
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#define CURBASE 0x70084
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#define CURPOS 0x70088
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/* VGA Registers */
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/* SMRAM Registers */
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#define SMRAM 0x10
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/* Graphics Control Registers */
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#define GR_INDEX 0x3CE
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#define GR_DATA 0x3CF
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#define GR10 0x10
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#define GR11 0x11
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/* CRT Controller Registers */
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#define CR_INDEX_MDA 0x3B4
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#define CR_INDEX_CGA 0x3D4
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#define CR_DATA_MDA 0x3B5
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#define CR_DATA_CGA 0x3D5
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#define CR30 0x30
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#define CR31 0x31
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#define CR32 0x32
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#define CR33 0x33
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#define CR35 0x35
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#define CR39 0x39
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#define CR40 0x40
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#define CR41 0x41
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#define CR42 0x42
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#define CR70 0x70
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#define CR80 0x80
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#define CR81 0x82
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/* Extended VGA Registers */
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/* General Control and Status Registers */
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#define ST00 0x3C2
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#define ST01_MDA 0x3BA
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#define ST01_CGA 0x3DA
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#define FRC_READ 0x3CA
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#define FRC_WRITE_MDA 0x3BA
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#define FRC_WRITE_CGA 0x3DA
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#define MSR_READ 0x3CC
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#define MSR_WRITE 0x3C2
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/* Sequencer Registers */
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#define SR_INDEX 0x3C4
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#define SR_DATA 0x3C5
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#define SR01 0x01
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#define SR02 0x02
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#define SR03 0x03
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#define SR04 0x04
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#define SR07 0x07
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/* Graphics Controller Registers */
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#define GR00 0x00
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#define GR01 0x01
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#define GR02 0x02
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#define GR03 0x03
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#define GR04 0x04
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#define GR05 0x05
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#define GR06 0x06
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#define GR07 0x07
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#define GR08 0x08
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/* Attribute Controller Registers */
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#define ATTR_WRITE 0x3C0
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#define ATTR_READ 0x3C1
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/* VGA Color Palette Registers */
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/* CLUT */
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#define CLUT_DATA 0x3C9 /* DACDATA */
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#define CLUT_INDEX_READ 0x3C7 /* DACRX */
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#define CLUT_INDEX_WRITE 0x3C8 /* DACWX */
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#define DACMASK 0x3C6
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/* CRT Controller Registers */
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#define CR00 0x00
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#define CR01 0x01
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#define CR02 0x02
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#define CR03 0x03
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#define CR04 0x04
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#define CR05 0x05
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#define CR06 0x06
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#define CR07 0x07
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#define CR08 0x08
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#define CR09 0x09
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#define CR0A 0x0A
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#define CR0B 0x0B
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#define CR0C 0x0C
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#define CR0D 0x0D
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#define CR0E 0x0E
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#define CR0F 0x0F
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#define CR10 0x10
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#define CR11 0x11
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#define CR12 0x12
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#define CR13 0x13
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#define CR14 0x14
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#define CR15 0x15
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#define CR16 0x16
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#define CR17 0x17
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#define CR18 0x18
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#endif /* __I810_REGS_H__ */
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