251 lines
6.4 KiB
C
251 lines
6.4 KiB
C
/*
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* linux/drivers/clocksource/acpi_pm.c
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*
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* This file contains the ACPI PM based clocksource.
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*
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* This code was largely moved from the i386 timer_pm.c file
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* which was (C) Dominik Brodowski <linux@brodo.de> 2003
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* and contained the following comments:
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*
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* Driver to use the Power Management Timer (PMTMR) available in some
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* southbridges as primary timing source for the Linux kernel.
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*
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* Based on parts of linux/drivers/acpi/hardware/hwtimer.c, timer_pit.c,
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* timer_hpet.c, and on Arjan van de Ven's implementation for 2.4.
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*
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* This file is licensed under the GPL v2.
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*/
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#include <linux/acpi_pmtmr.h>
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#include <linux/clocksource.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <asm/io.h>
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/*
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* The I/O port the PMTMR resides at.
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* The location is detected during setup_arch(),
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* in arch/i386/kernel/acpi/boot.c
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*/
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u32 pmtmr_ioport __read_mostly;
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static inline u32 read_pmtmr(void)
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{
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/* mask the output to 24 bits */
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return inl(pmtmr_ioport) & ACPI_PM_MASK;
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}
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u32 acpi_pm_read_verified(void)
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{
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u32 v1 = 0, v2 = 0, v3 = 0;
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/*
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* It has been reported that because of various broken
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* chipsets (ICH4, PIIX4 and PIIX4E) where the ACPI PM clock
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* source is not latched, you must read it multiple
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* times to ensure a safe value is read:
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*/
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do {
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v1 = read_pmtmr();
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v2 = read_pmtmr();
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v3 = read_pmtmr();
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} while (unlikely((v1 > v2 && v1 < v3) || (v2 > v3 && v2 < v1)
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|| (v3 > v1 && v3 < v2)));
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return v2;
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}
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static cycle_t acpi_pm_read(void)
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{
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return (cycle_t)read_pmtmr();
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}
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static struct clocksource clocksource_acpi_pm = {
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.name = "acpi_pm",
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.rating = 200,
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.read = acpi_pm_read,
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.mask = (cycle_t)ACPI_PM_MASK,
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.mult = 0, /*to be calculated*/
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.shift = 22,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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#ifdef CONFIG_PCI
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static int __devinitdata acpi_pm_good;
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static int __init acpi_pm_good_setup(char *__str)
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{
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acpi_pm_good = 1;
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return 1;
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}
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__setup("acpi_pm_good", acpi_pm_good_setup);
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static cycle_t acpi_pm_read_slow(void)
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{
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return (cycle_t)acpi_pm_read_verified();
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}
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static inline void acpi_pm_need_workaround(void)
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{
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clocksource_acpi_pm.read = acpi_pm_read_slow;
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clocksource_acpi_pm.rating = 120;
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}
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/*
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* PIIX4 Errata:
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*
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* The power management timer may return improper results when read.
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* Although the timer value settles properly after incrementing,
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* while incrementing there is a 3 ns window every 69.8 ns where the
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* timer value is indeterminate (a 4.2% chance that the data will be
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* incorrect when read). As a result, the ACPI free running count up
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* timer specification is violated due to erroneous reads.
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*/
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static void __devinit acpi_pm_check_blacklist(struct pci_dev *dev)
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{
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if (acpi_pm_good)
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return;
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/* the bug has been fixed in PIIX4M */
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if (dev->revision < 3) {
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printk(KERN_WARNING "* Found PM-Timer Bug on the chipset."
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" Due to workarounds for a bug,\n"
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"* this clock source is slow. Consider trying"
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" other clock sources\n");
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acpi_pm_need_workaround();
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}
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}
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
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acpi_pm_check_blacklist);
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static void __devinit acpi_pm_check_graylist(struct pci_dev *dev)
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{
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if (acpi_pm_good)
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return;
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printk(KERN_WARNING "* The chipset may have PM-Timer Bug. Due to"
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" workarounds for a bug,\n"
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"* this clock source is slow. If you are sure your timer"
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" does not have\n"
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"* this bug, please use \"acpi_pm_good\" to disable the"
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" workaround\n");
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acpi_pm_need_workaround();
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}
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0,
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acpi_pm_check_graylist);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_LE,
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acpi_pm_check_graylist);
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#endif
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#ifndef CONFIG_X86_64
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#include "mach_timer.h"
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#define PMTMR_EXPECTED_RATE \
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((CALIBRATE_LATCH * (PMTMR_TICKS_PER_SEC >> 10)) / (CLOCK_TICK_RATE>>10))
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/*
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* Some boards have the PMTMR running way too fast. We check
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* the PMTMR rate against PIT channel 2 to catch these cases.
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*/
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static int verify_pmtmr_rate(void)
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{
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cycle_t value1, value2;
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unsigned long count, delta;
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mach_prepare_counter();
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value1 = clocksource_acpi_pm.read();
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mach_countup(&count);
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value2 = clocksource_acpi_pm.read();
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delta = (value2 - value1) & ACPI_PM_MASK;
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/* Check that the PMTMR delta is within 5% of what we expect */
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if (delta < (PMTMR_EXPECTED_RATE * 19) / 20 ||
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delta > (PMTMR_EXPECTED_RATE * 21) / 20) {
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printk(KERN_INFO "PM-Timer running at invalid rate: %lu%% "
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"of normal - aborting.\n",
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100UL * delta / PMTMR_EXPECTED_RATE);
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return -1;
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}
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return 0;
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}
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#else
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#define verify_pmtmr_rate() (0)
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#endif
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/* Number of monotonicity checks to perform during initialization */
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#define ACPI_PM_MONOTONICITY_CHECKS 10
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/* Number of reads we try to get two different values */
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#define ACPI_PM_READ_CHECKS 10000
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static int __init init_acpi_pm_clocksource(void)
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{
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cycle_t value1, value2;
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unsigned int i, j = 0;
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if (!pmtmr_ioport)
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return -ENODEV;
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clocksource_acpi_pm.mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC,
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clocksource_acpi_pm.shift);
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/* "verify" this timing source: */
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for (j = 0; j < ACPI_PM_MONOTONICITY_CHECKS; j++) {
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udelay(100 * j);
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value1 = clocksource_acpi_pm.read();
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for (i = 0; i < ACPI_PM_READ_CHECKS; i++) {
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value2 = clocksource_acpi_pm.read();
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if (value2 == value1)
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continue;
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if (value2 > value1)
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break;
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if ((value2 < value1) && ((value2) < 0xFFF))
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break;
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printk(KERN_INFO "PM-Timer had inconsistent results:"
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" 0x%#llx, 0x%#llx - aborting.\n",
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value1, value2);
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return -EINVAL;
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}
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if (i == ACPI_PM_READ_CHECKS) {
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printk(KERN_INFO "PM-Timer failed consistency check "
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" (0x%#llx) - aborting.\n", value1);
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return -ENODEV;
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}
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}
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if (verify_pmtmr_rate() != 0)
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return -ENODEV;
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return clocksource_register(&clocksource_acpi_pm);
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}
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/* We use fs_initcall because we want the PCI fixups to have run
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* but we still need to load before device_initcall
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*/
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fs_initcall(init_acpi_pm_clocksource);
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/*
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* Allow an override of the IOPort. Stupid BIOSes do not tell us about
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* the PMTimer, but we might know where it is.
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*/
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static int __init parse_pmtmr(char *arg)
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{
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unsigned long base;
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if (strict_strtoul(arg, 16, &base))
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return -EINVAL;
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#ifdef CONFIG_X86_64
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if (base > UINT_MAX)
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return -ERANGE;
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#endif
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printk(KERN_INFO "PMTMR IOPort override: 0x%04x -> 0x%04lx\n",
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pmtmr_ioport, base);
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pmtmr_ioport = base;
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return 1;
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}
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__setup("pmtmr=", parse_pmtmr);
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