Ralf Baechle 10cc352907 [MIPS] Allow hardwiring of the CPU type to a single type for optimization. ... This saves a few k on systems which only ever ship with a single CPU type. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>		2007-10-11 23:46:15 +01:00
..
Makefile	[MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code.	2007-10-11 23:46:05 +01:00
c-r3k.c	…
c-r4k.c	[MIPS] Allow hardwiring of the CPU type to a single type for optimization.	2007-10-11 23:46:15 +01:00
c-tx39.c	[MIPS] Allow hardwiring of the CPU type to a single type for optimization.	2007-10-11 23:46:15 +01:00
cache.c	[MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code.	2007-10-11 23:46:05 +01:00
cerr-sb1.c	…
cex-gen.S	…
cex-sb1.S	…
dma-default.c	[MIPS] Allow hardwiring of the CPU type to a single type for optimization.	2007-10-11 23:46:15 +01:00
extable.c	…
fault.c	…
highmem.c	…
init.c	…
ioremap.c	…
pg-r4k.c	[MIPS] Allow hardwiring of the CPU type to a single type for optimization.	2007-10-11 23:46:15 +01:00
pg-sb1.c	[MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code.	2007-10-11 23:46:05 +01:00
pgtable-32.c	…
pgtable-64.c	…
pgtable.c	…
sc-ip22.c	…
sc-mips.c	[MIPS] MIPS32/MIPS64 S-cache fix and cleanup	2006-06-29 21:10:54 +01:00
sc-r5k.c	…
sc-rm7k.c	…
tlb-r3k.c	…
tlb-r4k.c	…
tlb-r8k.c	…
tlbex-fault.S	…
tlbex.c	[MIPS] Allow hardwiring of the CPU type to a single type for optimization.	2007-10-11 23:46:15 +01:00