163 lines
4.8 KiB
C
163 lines
4.8 KiB
C
/*
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* arch/arm/plat-omap/include/mach/clock.h
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*
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* Copyright (C) 2004 - 2005 Nokia corporation
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* Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
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* Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ARCH_ARM_OMAP_CLOCK_H
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#define __ARCH_ARM_OMAP_CLOCK_H
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struct module;
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struct clk;
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#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
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struct clksel_rate {
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u8 div;
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u32 val;
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u8 flags;
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};
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struct clksel {
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struct clk *parent;
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const struct clksel_rate *rates;
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};
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struct dpll_data {
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void __iomem *mult_div1_reg;
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u32 mult_mask;
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u32 div1_mask;
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u16 last_rounded_m;
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u8 last_rounded_n;
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unsigned long last_rounded_rate;
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unsigned int rate_tolerance;
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u16 max_multiplier;
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u8 max_divider;
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u32 max_tolerance;
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# if defined(CONFIG_ARCH_OMAP3)
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u8 modes;
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void __iomem *control_reg;
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u32 enable_mask;
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u8 auto_recal_bit;
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u8 recal_en_bit;
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u8 recal_st_bit;
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void __iomem *autoidle_reg;
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u32 autoidle_mask;
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void __iomem *idlest_reg;
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u8 idlest_bit;
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# endif
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};
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#endif
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struct clk {
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struct list_head node;
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struct module *owner;
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const char *name;
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int id;
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struct clk *parent;
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unsigned long rate;
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__u32 flags;
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void __iomem *enable_reg;
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__u8 enable_bit;
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__s8 usecount;
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void (*recalc)(struct clk *);
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int (*set_rate)(struct clk *, unsigned long);
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long (*round_rate)(struct clk *, unsigned long);
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void (*init)(struct clk *);
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int (*enable)(struct clk *);
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void (*disable)(struct clk *);
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#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
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u8 fixed_div;
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void __iomem *clksel_reg;
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u32 clksel_mask;
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const struct clksel *clksel;
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struct dpll_data *dpll_data;
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#else
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__u8 rate_offset;
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__u8 src_offset;
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#endif
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#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
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struct dentry *dent; /* For visible tree hierarchy */
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#endif
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};
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struct cpufreq_frequency_table;
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struct clk_functions {
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int (*clk_enable)(struct clk *clk);
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void (*clk_disable)(struct clk *clk);
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long (*clk_round_rate)(struct clk *clk, unsigned long rate);
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int (*clk_set_rate)(struct clk *clk, unsigned long rate);
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int (*clk_set_parent)(struct clk *clk, struct clk *parent);
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struct clk * (*clk_get_parent)(struct clk *clk);
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void (*clk_allow_idle)(struct clk *clk);
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void (*clk_deny_idle)(struct clk *clk);
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void (*clk_disable_unused)(struct clk *clk);
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#ifdef CONFIG_CPU_FREQ
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void (*clk_init_cpufreq_table)(struct cpufreq_frequency_table **);
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#endif
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};
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extern unsigned int mpurate;
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extern int clk_init(struct clk_functions * custom_clocks);
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extern int clk_register(struct clk *clk);
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extern void clk_unregister(struct clk *clk);
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extern void propagate_rate(struct clk *clk);
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extern void recalculate_root_clocks(void);
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extern void followparent_recalc(struct clk * clk);
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extern void clk_allow_idle(struct clk *clk);
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extern void clk_deny_idle(struct clk *clk);
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extern int clk_get_usecount(struct clk *clk);
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extern void clk_enable_init_clocks(void);
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/* Clock flags */
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#define RATE_CKCTL (1 << 0) /* Main fixed ratio clocks */
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#define RATE_FIXED (1 << 1) /* Fixed clock rate */
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#define RATE_PROPAGATES (1 << 2) /* Program children too */
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#define VIRTUAL_CLOCK (1 << 3) /* Composite clock from table */
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#define ALWAYS_ENABLED (1 << 4) /* Clock cannot be disabled */
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#define ENABLE_REG_32BIT (1 << 5) /* Use 32-bit access */
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#define VIRTUAL_IO_ADDRESS (1 << 6) /* Clock in virtual address */
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#define CLOCK_IDLE_CONTROL (1 << 7)
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#define CLOCK_NO_IDLE_PARENT (1 << 8)
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#define DELAYED_APP (1 << 9) /* Delay application of clock */
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#define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */
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#define ENABLE_ON_INIT (1 << 11) /* Enable upon framework init */
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#define INVERT_ENABLE (1 << 12) /* 0 enables, 1 disables */
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/* bits 13-20 are currently free */
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#define CLOCK_IN_OMAP310 (1 << 21)
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#define CLOCK_IN_OMAP730 (1 << 22)
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#define CLOCK_IN_OMAP1510 (1 << 23)
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#define CLOCK_IN_OMAP16XX (1 << 24)
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#define CLOCK_IN_OMAP242X (1 << 25)
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#define CLOCK_IN_OMAP243X (1 << 26)
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#define CLOCK_IN_OMAP343X (1 << 27) /* clocks common to all 343X */
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#define PARENT_CONTROLS_CLOCK (1 << 28)
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#define CLOCK_IN_OMAP3430ES1 (1 << 29) /* 3430ES1 clocks only */
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#define CLOCK_IN_OMAP3430ES2 (1 << 30) /* 3430ES2 clocks only */
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/* Clksel_rate flags */
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#define DEFAULT_RATE (1 << 0)
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#define RATE_IN_242X (1 << 1)
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#define RATE_IN_243X (1 << 2)
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#define RATE_IN_343X (1 << 3) /* rates common to all 343X */
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#define RATE_IN_3430ES2 (1 << 4) /* 3430ES2 rates only */
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#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
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/* CM_CLKSEL2_PLL.CORE_CLK_SRC options (24XX) */
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#define CORE_CLK_SRC_32K 0
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#define CORE_CLK_SRC_DPLL 1
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#define CORE_CLK_SRC_DPLL_X2 2
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#endif
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