329 lines
7.9 KiB
C
329 lines
7.9 KiB
C
/*
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* Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* EXYNOS - Power Management support
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*
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* Based on arch/arm/mach-s3c2410/pm.c
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* Copyright (c) 2006 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/suspend.h>
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#include <linux/syscore_ops.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <asm/cacheflush.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <asm/smp_scu.h>
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#include <plat/cpu.h>
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#include <plat/pm.h>
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#include <plat/pll.h>
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#include <plat/regs-srom.h>
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#include <mach/regs-irq.h>
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#include <mach/regs-gpio.h>
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#include <mach/regs-clock.h>
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#include <mach/regs-pmu.h>
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#include <mach/pm-core.h>
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#include <mach/pmu.h>
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static struct sleep_save exynos4_set_clksrc[] = {
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{ .reg = EXYNOS4_CLKSRC_MASK_TOP , .val = 0x00000001, },
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{ .reg = EXYNOS4_CLKSRC_MASK_CAM , .val = 0x11111111, },
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{ .reg = EXYNOS4_CLKSRC_MASK_TV , .val = 0x00000111, },
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{ .reg = EXYNOS4_CLKSRC_MASK_LCD0 , .val = 0x00001111, },
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{ .reg = EXYNOS4_CLKSRC_MASK_MAUDIO , .val = 0x00000001, },
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{ .reg = EXYNOS4_CLKSRC_MASK_FSYS , .val = 0x01011111, },
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{ .reg = EXYNOS4_CLKSRC_MASK_PERIL0 , .val = 0x01111111, },
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{ .reg = EXYNOS4_CLKSRC_MASK_PERIL1 , .val = 0x01110111, },
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{ .reg = EXYNOS4_CLKSRC_MASK_DMC , .val = 0x00010000, },
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};
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static struct sleep_save exynos4210_set_clksrc[] = {
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{ .reg = EXYNOS4210_CLKSRC_MASK_LCD1 , .val = 0x00001111, },
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};
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static struct sleep_save exynos4_epll_save[] = {
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SAVE_ITEM(EXYNOS4_EPLL_CON0),
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SAVE_ITEM(EXYNOS4_EPLL_CON1),
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};
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static struct sleep_save exynos4_vpll_save[] = {
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SAVE_ITEM(EXYNOS4_VPLL_CON0),
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SAVE_ITEM(EXYNOS4_VPLL_CON1),
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};
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static struct sleep_save exynos_core_save[] = {
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/* SROM side */
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SAVE_ITEM(S5P_SROM_BW),
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SAVE_ITEM(S5P_SROM_BC0),
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SAVE_ITEM(S5P_SROM_BC1),
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SAVE_ITEM(S5P_SROM_BC2),
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SAVE_ITEM(S5P_SROM_BC3),
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};
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/* For Cortex-A9 Diagnostic and Power control register */
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static unsigned int save_arm_register[2];
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static int exynos_cpu_suspend(unsigned long arg)
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{
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#ifdef CONFIG_CACHE_L2X0
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outer_flush_all();
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#endif
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/* issue the standby signal into the pm unit. */
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cpu_do_idle();
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/* we should never get past here */
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panic("sleep resumed to originator?");
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}
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static void exynos_pm_prepare(void)
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{
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unsigned int tmp;
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s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
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if (!soc_is_exynos5250()) {
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s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save));
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s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save));
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} else {
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/* Disable USE_RETENTION of JPEG_MEM_OPTION */
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tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION);
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tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
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__raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
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}
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/* Set value of power down register for sleep mode */
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exynos_sys_powerdown_conf(SYS_SLEEP);
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__raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
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/* ensure at least INFORM0 has the resume address */
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__raw_writel(virt_to_phys(s3c_cpu_resume), S5P_INFORM0);
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/* Before enter central sequence mode, clock src register have to set */
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if (!soc_is_exynos5250())
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s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc));
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if (soc_is_exynos4210())
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s3c_pm_do_restore_core(exynos4210_set_clksrc, ARRAY_SIZE(exynos4210_set_clksrc));
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}
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static int exynos_pm_add(struct device *dev, struct subsys_interface *sif)
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{
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pm_cpu_prep = exynos_pm_prepare;
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pm_cpu_sleep = exynos_cpu_suspend;
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return 0;
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}
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static unsigned long pll_base_rate;
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static void exynos4_restore_pll(void)
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{
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unsigned long pll_con, locktime, lockcnt;
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unsigned long pll_in_rate;
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unsigned int p_div, epll_wait = 0, vpll_wait = 0;
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if (pll_base_rate == 0)
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return;
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pll_in_rate = pll_base_rate;
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/* EPLL */
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pll_con = exynos4_epll_save[0].val;
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if (pll_con & (1 << 31)) {
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pll_con &= (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT);
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p_div = (pll_con >> PLL46XX_PDIV_SHIFT);
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pll_in_rate /= 1000000;
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locktime = (3000 / pll_in_rate) * p_div;
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lockcnt = locktime * 10000 / (10000 / pll_in_rate);
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__raw_writel(lockcnt, EXYNOS4_EPLL_LOCK);
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s3c_pm_do_restore_core(exynos4_epll_save,
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ARRAY_SIZE(exynos4_epll_save));
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epll_wait = 1;
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}
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pll_in_rate = pll_base_rate;
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/* VPLL */
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pll_con = exynos4_vpll_save[0].val;
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if (pll_con & (1 << 31)) {
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pll_in_rate /= 1000000;
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/* 750us */
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locktime = 750;
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lockcnt = locktime * 10000 / (10000 / pll_in_rate);
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__raw_writel(lockcnt, EXYNOS4_VPLL_LOCK);
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s3c_pm_do_restore_core(exynos4_vpll_save,
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ARRAY_SIZE(exynos4_vpll_save));
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vpll_wait = 1;
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}
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/* Wait PLL locking */
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do {
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if (epll_wait) {
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pll_con = __raw_readl(EXYNOS4_EPLL_CON0);
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if (pll_con & (1 << EXYNOS4_EPLLCON0_LOCKED_SHIFT))
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epll_wait = 0;
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}
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if (vpll_wait) {
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pll_con = __raw_readl(EXYNOS4_VPLL_CON0);
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if (pll_con & (1 << EXYNOS4_VPLLCON0_LOCKED_SHIFT))
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vpll_wait = 0;
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}
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} while (epll_wait || vpll_wait);
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}
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static struct subsys_interface exynos_pm_interface = {
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.name = "exynos_pm",
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.subsys = &exynos_subsys,
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.add_dev = exynos_pm_add,
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};
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static __init int exynos_pm_drvinit(void)
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{
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struct clk *pll_base;
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unsigned int tmp;
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s3c_pm_init();
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/* All wakeup disable */
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tmp = __raw_readl(S5P_WAKEUP_MASK);
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tmp |= ((0xFF << 8) | (0x1F << 1));
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__raw_writel(tmp, S5P_WAKEUP_MASK);
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if (!soc_is_exynos5250()) {
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pll_base = clk_get(NULL, "xtal");
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if (!IS_ERR(pll_base)) {
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pll_base_rate = clk_get_rate(pll_base);
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clk_put(pll_base);
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}
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}
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return subsys_interface_register(&exynos_pm_interface);
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}
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arch_initcall(exynos_pm_drvinit);
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static int exynos_pm_suspend(void)
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{
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unsigned long tmp;
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/* Setting Central Sequence Register for power down mode */
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tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
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tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
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__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
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/* Setting SEQ_OPTION register */
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tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
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__raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
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if (!soc_is_exynos5250()) {
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/* Save Power control register */
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asm ("mrc p15, 0, %0, c15, c0, 0"
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: "=r" (tmp) : : "cc");
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save_arm_register[0] = tmp;
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/* Save Diagnostic register */
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asm ("mrc p15, 0, %0, c15, c0, 1"
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: "=r" (tmp) : : "cc");
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save_arm_register[1] = tmp;
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}
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return 0;
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}
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static void exynos_pm_resume(void)
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{
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unsigned long tmp;
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/*
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* If PMU failed while entering sleep mode, WFI will be
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* ignored by PMU and then exiting cpu_do_idle().
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* S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
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* in this situation.
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*/
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tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
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if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
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tmp |= S5P_CENTRAL_LOWPWR_CFG;
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__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
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/* No need to perform below restore code */
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goto early_wakeup;
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}
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if (!soc_is_exynos5250()) {
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/* Restore Power control register */
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tmp = save_arm_register[0];
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asm volatile ("mcr p15, 0, %0, c15, c0, 0"
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: : "r" (tmp)
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: "cc");
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/* Restore Diagnostic register */
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tmp = save_arm_register[1];
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asm volatile ("mcr p15, 0, %0, c15, c0, 1"
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: : "r" (tmp)
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: "cc");
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}
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/* For release retention */
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__raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
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__raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
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__raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
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__raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
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__raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
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__raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
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__raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
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s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
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if (!soc_is_exynos5250()) {
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exynos4_restore_pll();
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#ifdef CONFIG_SMP
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scu_enable(S5P_VA_SCU);
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#endif
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}
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early_wakeup:
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return;
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}
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static struct syscore_ops exynos_pm_syscore_ops = {
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.suspend = exynos_pm_suspend,
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.resume = exynos_pm_resume,
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};
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static __init int exynos_pm_syscore_init(void)
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{
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register_syscore_ops(&exynos_pm_syscore_ops);
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return 0;
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}
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arch_initcall(exynos_pm_syscore_init);
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