298 lines
8.1 KiB
C
298 lines
8.1 KiB
C
/*
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* Interrupt handling for Marvell mv64360/mv64460 host bridges (Discovery)
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*
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* Author: Dale Farnsworth <dale@farnsworth.org>
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*
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* 2007 (c) MontaVista, Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/spinlock.h>
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#include <asm/byteorder.h>
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#include <asm/io.h>
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#include <asm/prom.h>
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#include <asm/irq.h>
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#include "mv64x60.h"
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/* Interrupt Controller Interface Registers */
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#define MV64X60_IC_MAIN_CAUSE_LO 0x0004
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#define MV64X60_IC_MAIN_CAUSE_HI 0x000c
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#define MV64X60_IC_CPU0_INTR_MASK_LO 0x0014
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#define MV64X60_IC_CPU0_INTR_MASK_HI 0x001c
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#define MV64X60_IC_CPU0_SELECT_CAUSE 0x0024
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#define MV64X60_HIGH_GPP_GROUPS 0x0f000000
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#define MV64X60_SELECT_CAUSE_HIGH 0x40000000
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/* General Purpose Pins Controller Interface Registers */
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#define MV64x60_GPP_INTR_CAUSE 0x0008
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#define MV64x60_GPP_INTR_MASK 0x000c
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#define MV64x60_LEVEL1_LOW 0
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#define MV64x60_LEVEL1_HIGH 1
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#define MV64x60_LEVEL1_GPP 2
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#define MV64x60_LEVEL1_MASK 0x00000060
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#define MV64x60_LEVEL1_OFFSET 5
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#define MV64x60_LEVEL2_MASK 0x0000001f
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#define MV64x60_NUM_IRQS 96
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static DEFINE_SPINLOCK(mv64x60_lock);
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static void __iomem *mv64x60_irq_reg_base;
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static void __iomem *mv64x60_gpp_reg_base;
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/*
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* Interrupt Controller Handling
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*
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* The interrupt controller handles three groups of interrupts:
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* main low: IRQ0-IRQ31
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* main high: IRQ32-IRQ63
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* gpp: IRQ64-IRQ95
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*
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* This code handles interrupts in two levels. Level 1 selects the
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* interrupt group, and level 2 selects an IRQ within that group.
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* Each group has its own irq_chip structure.
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*/
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static u32 mv64x60_cached_low_mask;
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static u32 mv64x60_cached_high_mask = MV64X60_HIGH_GPP_GROUPS;
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static u32 mv64x60_cached_gpp_mask;
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static struct irq_domain *mv64x60_irq_host;
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/*
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* mv64x60_chip_low functions
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*/
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static void mv64x60_mask_low(struct irq_data *d)
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{
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int level2 = irqd_to_hwirq(d) & MV64x60_LEVEL2_MASK;
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unsigned long flags;
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spin_lock_irqsave(&mv64x60_lock, flags);
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mv64x60_cached_low_mask &= ~(1 << level2);
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out_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_LO,
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mv64x60_cached_low_mask);
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spin_unlock_irqrestore(&mv64x60_lock, flags);
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(void)in_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_LO);
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}
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static void mv64x60_unmask_low(struct irq_data *d)
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{
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int level2 = irqd_to_hwirq(d) & MV64x60_LEVEL2_MASK;
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unsigned long flags;
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spin_lock_irqsave(&mv64x60_lock, flags);
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mv64x60_cached_low_mask |= 1 << level2;
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out_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_LO,
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mv64x60_cached_low_mask);
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spin_unlock_irqrestore(&mv64x60_lock, flags);
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(void)in_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_LO);
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}
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static struct irq_chip mv64x60_chip_low = {
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.name = "mv64x60_low",
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.irq_mask = mv64x60_mask_low,
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.irq_mask_ack = mv64x60_mask_low,
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.irq_unmask = mv64x60_unmask_low,
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};
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/*
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* mv64x60_chip_high functions
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*/
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static void mv64x60_mask_high(struct irq_data *d)
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{
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int level2 = irqd_to_hwirq(d) & MV64x60_LEVEL2_MASK;
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unsigned long flags;
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spin_lock_irqsave(&mv64x60_lock, flags);
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mv64x60_cached_high_mask &= ~(1 << level2);
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out_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_HI,
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mv64x60_cached_high_mask);
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spin_unlock_irqrestore(&mv64x60_lock, flags);
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(void)in_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_HI);
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}
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static void mv64x60_unmask_high(struct irq_data *d)
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{
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int level2 = irqd_to_hwirq(d) & MV64x60_LEVEL2_MASK;
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unsigned long flags;
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spin_lock_irqsave(&mv64x60_lock, flags);
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mv64x60_cached_high_mask |= 1 << level2;
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out_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_HI,
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mv64x60_cached_high_mask);
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spin_unlock_irqrestore(&mv64x60_lock, flags);
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(void)in_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_HI);
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}
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static struct irq_chip mv64x60_chip_high = {
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.name = "mv64x60_high",
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.irq_mask = mv64x60_mask_high,
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.irq_mask_ack = mv64x60_mask_high,
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.irq_unmask = mv64x60_unmask_high,
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};
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/*
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* mv64x60_chip_gpp functions
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*/
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static void mv64x60_mask_gpp(struct irq_data *d)
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{
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int level2 = irqd_to_hwirq(d) & MV64x60_LEVEL2_MASK;
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unsigned long flags;
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spin_lock_irqsave(&mv64x60_lock, flags);
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mv64x60_cached_gpp_mask &= ~(1 << level2);
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out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK,
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mv64x60_cached_gpp_mask);
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spin_unlock_irqrestore(&mv64x60_lock, flags);
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(void)in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK);
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}
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static void mv64x60_mask_ack_gpp(struct irq_data *d)
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{
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int level2 = irqd_to_hwirq(d) & MV64x60_LEVEL2_MASK;
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unsigned long flags;
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spin_lock_irqsave(&mv64x60_lock, flags);
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mv64x60_cached_gpp_mask &= ~(1 << level2);
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out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK,
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mv64x60_cached_gpp_mask);
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out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_CAUSE,
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~(1 << level2));
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spin_unlock_irqrestore(&mv64x60_lock, flags);
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(void)in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_CAUSE);
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}
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static void mv64x60_unmask_gpp(struct irq_data *d)
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{
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int level2 = irqd_to_hwirq(d) & MV64x60_LEVEL2_MASK;
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unsigned long flags;
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spin_lock_irqsave(&mv64x60_lock, flags);
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mv64x60_cached_gpp_mask |= 1 << level2;
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out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK,
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mv64x60_cached_gpp_mask);
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spin_unlock_irqrestore(&mv64x60_lock, flags);
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(void)in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK);
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}
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static struct irq_chip mv64x60_chip_gpp = {
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.name = "mv64x60_gpp",
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.irq_mask = mv64x60_mask_gpp,
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.irq_mask_ack = mv64x60_mask_ack_gpp,
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.irq_unmask = mv64x60_unmask_gpp,
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};
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/*
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* mv64x60_host_ops functions
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*/
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static struct irq_chip *mv64x60_chips[] = {
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[MV64x60_LEVEL1_LOW] = &mv64x60_chip_low,
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[MV64x60_LEVEL1_HIGH] = &mv64x60_chip_high,
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[MV64x60_LEVEL1_GPP] = &mv64x60_chip_gpp,
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};
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static int mv64x60_host_map(struct irq_domain *h, unsigned int virq,
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irq_hw_number_t hwirq)
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{
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int level1;
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irq_set_status_flags(virq, IRQ_LEVEL);
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level1 = (hwirq & MV64x60_LEVEL1_MASK) >> MV64x60_LEVEL1_OFFSET;
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BUG_ON(level1 > MV64x60_LEVEL1_GPP);
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irq_set_chip_and_handler(virq, mv64x60_chips[level1],
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handle_level_irq);
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return 0;
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}
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static struct irq_domain_ops mv64x60_host_ops = {
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.map = mv64x60_host_map,
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};
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/*
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* Global functions
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*/
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void __init mv64x60_init_irq(void)
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{
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struct device_node *np;
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phys_addr_t paddr;
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unsigned int size;
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const unsigned int *reg;
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unsigned long flags;
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np = of_find_compatible_node(NULL, NULL, "marvell,mv64360-gpp");
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reg = of_get_property(np, "reg", &size);
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paddr = of_translate_address(np, reg);
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mv64x60_gpp_reg_base = ioremap(paddr, reg[1]);
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of_node_put(np);
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np = of_find_compatible_node(NULL, NULL, "marvell,mv64360-pic");
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reg = of_get_property(np, "reg", &size);
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paddr = of_translate_address(np, reg);
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mv64x60_irq_reg_base = ioremap(paddr, reg[1]);
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mv64x60_irq_host = irq_domain_add_linear(np, MV64x60_NUM_IRQS,
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&mv64x60_host_ops, NULL);
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spin_lock_irqsave(&mv64x60_lock, flags);
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out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK,
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mv64x60_cached_gpp_mask);
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out_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_LO,
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mv64x60_cached_low_mask);
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out_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_HI,
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mv64x60_cached_high_mask);
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out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_CAUSE, 0);
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out_le32(mv64x60_irq_reg_base + MV64X60_IC_MAIN_CAUSE_LO, 0);
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out_le32(mv64x60_irq_reg_base + MV64X60_IC_MAIN_CAUSE_HI, 0);
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spin_unlock_irqrestore(&mv64x60_lock, flags);
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}
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unsigned int mv64x60_get_irq(void)
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{
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u32 cause;
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int level1;
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irq_hw_number_t hwirq;
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int virq = NO_IRQ;
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cause = in_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_SELECT_CAUSE);
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if (cause & MV64X60_SELECT_CAUSE_HIGH) {
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cause &= mv64x60_cached_high_mask;
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level1 = MV64x60_LEVEL1_HIGH;
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if (cause & MV64X60_HIGH_GPP_GROUPS) {
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cause = in_le32(mv64x60_gpp_reg_base +
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MV64x60_GPP_INTR_CAUSE);
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cause &= mv64x60_cached_gpp_mask;
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level1 = MV64x60_LEVEL1_GPP;
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}
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} else {
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cause &= mv64x60_cached_low_mask;
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level1 = MV64x60_LEVEL1_LOW;
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}
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if (cause) {
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hwirq = (level1 << MV64x60_LEVEL1_OFFSET) | __ilog2(cause);
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virq = irq_linear_revmap(mv64x60_irq_host, hwirq);
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}
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return virq;
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}
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