243 lines
8.5 KiB
C
243 lines
8.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __HD64570_H
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#define __HD64570_H
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/* SCA HD64570 register definitions - all addresses for mode 0 (8086 MPU)
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and 1 (64180 MPU). For modes 2 and 3, XOR the address with 0x01.
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Source: HD64570 SCA User's Manual
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*/
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/* SCA Control Registers */
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#define LPR 0x00 /* Low Power */
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/* Wait controller registers */
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#define PABR0 0x02 /* Physical Address Boundary 0 */
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#define PABR1 0x03 /* Physical Address Boundary 1 */
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#define WCRL 0x04 /* Wait Control L */
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#define WCRM 0x05 /* Wait Control M */
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#define WCRH 0x06 /* Wait Control H */
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#define PCR 0x08 /* DMA Priority Control */
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#define DMER 0x09 /* DMA Master Enable */
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/* Interrupt registers */
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#define ISR0 0x10 /* Interrupt Status 0 */
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#define ISR1 0x11 /* Interrupt Status 1 */
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#define ISR2 0x12 /* Interrupt Status 2 */
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#define IER0 0x14 /* Interrupt Enable 0 */
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#define IER1 0x15 /* Interrupt Enable 1 */
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#define IER2 0x16 /* Interrupt Enable 2 */
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#define ITCR 0x18 /* Interrupt Control */
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#define IVR 0x1A /* Interrupt Vector */
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#define IMVR 0x1C /* Interrupt Modified Vector */
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/* MSCI channel (port) 0 registers - offset 0x20
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MSCI channel (port) 1 registers - offset 0x40 */
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#define MSCI0_OFFSET 0x20
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#define MSCI1_OFFSET 0x40
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#define TRBL 0x00 /* TX/RX buffer L */
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#define TRBH 0x01 /* TX/RX buffer H */
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#define ST0 0x02 /* Status 0 */
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#define ST1 0x03 /* Status 1 */
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#define ST2 0x04 /* Status 2 */
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#define ST3 0x05 /* Status 3 */
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#define FST 0x06 /* Frame Status */
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#define IE0 0x08 /* Interrupt Enable 0 */
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#define IE1 0x09 /* Interrupt Enable 1 */
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#define IE2 0x0A /* Interrupt Enable 2 */
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#define FIE 0x0B /* Frame Interrupt Enable */
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#define CMD 0x0C /* Command */
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#define MD0 0x0E /* Mode 0 */
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#define MD1 0x0F /* Mode 1 */
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#define MD2 0x10 /* Mode 2 */
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#define CTL 0x11 /* Control */
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#define SA0 0x12 /* Sync/Address 0 */
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#define SA1 0x13 /* Sync/Address 1 */
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#define IDL 0x14 /* Idle Pattern */
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#define TMC 0x15 /* Time Constant */
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#define RXS 0x16 /* RX Clock Source */
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#define TXS 0x17 /* TX Clock Source */
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#define TRC0 0x18 /* TX Ready Control 0 */
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#define TRC1 0x19 /* TX Ready Control 1 */
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#define RRC 0x1A /* RX Ready Control */
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#define CST0 0x1C /* Current Status 0 */
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#define CST1 0x1D /* Current Status 1 */
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/* Timer channel 0 (port 0 RX) registers - offset 0x60
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Timer channel 1 (port 0 TX) registers - offset 0x68
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Timer channel 2 (port 1 RX) registers - offset 0x70
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Timer channel 3 (port 1 TX) registers - offset 0x78
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*/
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#define TIMER0RX_OFFSET 0x60
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#define TIMER0TX_OFFSET 0x68
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#define TIMER1RX_OFFSET 0x70
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#define TIMER1TX_OFFSET 0x78
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#define TCNTL 0x00 /* Up-counter L */
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#define TCNTH 0x01 /* Up-counter H */
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#define TCONRL 0x02 /* Constant L */
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#define TCONRH 0x03 /* Constant H */
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#define TCSR 0x04 /* Control/Status */
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#define TEPR 0x05 /* Expand Prescale */
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/* DMA channel 0 (port 0 RX) registers - offset 0x80
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DMA channel 1 (port 0 TX) registers - offset 0xA0
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DMA channel 2 (port 1 RX) registers - offset 0xC0
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DMA channel 3 (port 1 TX) registers - offset 0xE0
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*/
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#define DMAC0RX_OFFSET 0x80
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#define DMAC0TX_OFFSET 0xA0
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#define DMAC1RX_OFFSET 0xC0
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#define DMAC1TX_OFFSET 0xE0
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#define BARL 0x00 /* Buffer Address L (chained block) */
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#define BARH 0x01 /* Buffer Address H (chained block) */
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#define BARB 0x02 /* Buffer Address B (chained block) */
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#define DARL 0x00 /* RX Destination Addr L (single block) */
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#define DARH 0x01 /* RX Destination Addr H (single block) */
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#define DARB 0x02 /* RX Destination Addr B (single block) */
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#define SARL 0x04 /* TX Source Address L (single block) */
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#define SARH 0x05 /* TX Source Address H (single block) */
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#define SARB 0x06 /* TX Source Address B (single block) */
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#define CPB 0x06 /* Chain Pointer Base (chained block) */
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#define CDAL 0x08 /* Current Descriptor Addr L (chained block) */
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#define CDAH 0x09 /* Current Descriptor Addr H (chained block) */
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#define EDAL 0x0A /* Error Descriptor Addr L (chained block) */
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#define EDAH 0x0B /* Error Descriptor Addr H (chained block) */
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#define BFLL 0x0C /* RX Receive Buffer Length L (chained block)*/
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#define BFLH 0x0D /* RX Receive Buffer Length H (chained block)*/
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#define BCRL 0x0E /* Byte Count L */
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#define BCRH 0x0F /* Byte Count H */
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#define DSR 0x10 /* DMA Status */
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#define DSR_RX(node) (DSR + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))
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#define DSR_TX(node) (DSR + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))
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#define DMR 0x11 /* DMA Mode */
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#define DMR_RX(node) (DMR + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))
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#define DMR_TX(node) (DMR + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))
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#define FCT 0x13 /* Frame End Interrupt Counter */
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#define FCT_RX(node) (FCT + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))
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#define FCT_TX(node) (FCT + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))
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#define DIR 0x14 /* DMA Interrupt Enable */
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#define DIR_RX(node) (DIR + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))
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#define DIR_TX(node) (DIR + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))
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#define DCR 0x15 /* DMA Command */
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#define DCR_RX(node) (DCR + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))
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#define DCR_TX(node) (DCR + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))
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/* Descriptor Structure */
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typedef struct {
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u16 cp; /* Chain Pointer */
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u32 bp; /* Buffer Pointer (24 bits) */
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u16 len; /* Data Length */
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u8 stat; /* Status */
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u8 unused; /* pads to 2-byte boundary */
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}__packed pkt_desc;
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/* Packet Descriptor Status bits */
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#define ST_TX_EOM 0x80 /* End of frame */
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#define ST_TX_EOT 0x01 /* End of transmission */
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#define ST_RX_EOM 0x80 /* End of frame */
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#define ST_RX_SHORT 0x40 /* Short frame */
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#define ST_RX_ABORT 0x20 /* Abort */
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#define ST_RX_RESBIT 0x10 /* Residual bit */
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#define ST_RX_OVERRUN 0x08 /* Overrun */
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#define ST_RX_CRC 0x04 /* CRC */
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#define ST_ERROR_MASK 0x7C
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#define DIR_EOTE 0x80 /* Transfer completed */
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#define DIR_EOME 0x40 /* Frame Transfer Completed (chained-block) */
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#define DIR_BOFE 0x20 /* Buffer Overflow/Underflow (chained-block)*/
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#define DIR_COFE 0x10 /* Counter Overflow (chained-block) */
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#define DSR_EOT 0x80 /* Transfer completed */
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#define DSR_EOM 0x40 /* Frame Transfer Completed (chained-block) */
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#define DSR_BOF 0x20 /* Buffer Overflow/Underflow (chained-block)*/
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#define DSR_COF 0x10 /* Counter Overflow (chained-block) */
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#define DSR_DE 0x02 /* DMA Enable */
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#define DSR_DWE 0x01 /* DMA Write Disable */
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/* DMA Master Enable Register (DMER) bits */
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#define DMER_DME 0x80 /* DMA Master Enable */
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#define CMD_RESET 0x21 /* Reset Channel */
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#define CMD_TX_ENABLE 0x02 /* Start transmitter */
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#define CMD_RX_ENABLE 0x12 /* Start receiver */
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#define MD0_HDLC 0x80 /* Bit-sync HDLC mode */
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#define MD0_CRC_ENA 0x04 /* Enable CRC code calculation */
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#define MD0_CRC_CCITT 0x02 /* CCITT CRC instead of CRC-16 */
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#define MD0_CRC_PR1 0x01 /* Initial all-ones instead of all-zeros */
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#define MD0_CRC_NONE 0x00
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#define MD0_CRC_16_0 0x04
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#define MD0_CRC_16 0x05
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#define MD0_CRC_ITU_0 0x06
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#define MD0_CRC_ITU 0x07
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#define MD2_NRZ 0x00
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#define MD2_NRZI 0x20
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#define MD2_MANCHESTER 0x80
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#define MD2_FM_MARK 0xA0
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#define MD2_FM_SPACE 0xC0
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#define MD2_LOOPBACK 0x03 /* Local data Loopback */
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#define CTL_NORTS 0x01
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#define CTL_IDLE 0x10 /* Transmit an idle pattern */
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#define CTL_UDRNC 0x20 /* Idle after CRC or FCS+flag transmission */
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#define ST0_TXRDY 0x02 /* TX ready */
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#define ST0_RXRDY 0x01 /* RX ready */
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#define ST1_UDRN 0x80 /* MSCI TX underrun */
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#define ST1_CDCD 0x04 /* DCD level changed */
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#define ST3_CTS 0x08 /* modem input - /CTS */
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#define ST3_DCD 0x04 /* modem input - /DCD */
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#define IE0_TXINT 0x80 /* TX INT MSCI interrupt enable */
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#define IE0_RXINTA 0x40 /* RX INT A MSCI interrupt enable */
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#define IE1_UDRN 0x80 /* TX underrun MSCI interrupt enable */
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#define IE1_CDCD 0x04 /* DCD level changed */
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#define DCR_ABORT 0x01 /* Software abort command */
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#define DCR_CLEAR_EOF 0x02 /* Clear EOF interrupt */
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/* TX and RX Clock Source - RXS and TXS */
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#define CLK_BRG_MASK 0x0F
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#define CLK_LINE_RX 0x00 /* TX/RX clock line input */
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#define CLK_LINE_TX 0x00 /* TX/RX line input */
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#define CLK_BRG_RX 0x40 /* internal baud rate generator */
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#define CLK_BRG_TX 0x40 /* internal baud rate generator */
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#define CLK_RXCLK_TX 0x60 /* TX clock from RX clock */
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#endif
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