296 lines
7.9 KiB
C
296 lines
7.9 KiB
C
/*
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* SN2 Platform specific SMP Support
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/spinlock.h>
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#include <linux/threads.h>
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#include <linux/sched.h>
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#include <linux/smp.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/mmzone.h>
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#include <linux/module.h>
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#include <linux/bitops.h>
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#include <linux/nodemask.h>
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#include <asm/processor.h>
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#include <asm/irq.h>
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#include <asm/sal.h>
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#include <asm/system.h>
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#include <asm/delay.h>
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#include <asm/io.h>
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#include <asm/smp.h>
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#include <asm/tlb.h>
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#include <asm/numa.h>
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#include <asm/hw_irq.h>
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#include <asm/current.h>
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#include <asm/sn/sn_cpuid.h>
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#include <asm/sn/sn_sal.h>
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#include <asm/sn/addrs.h>
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#include <asm/sn/shub_mmr.h>
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#include <asm/sn/nodepda.h>
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#include <asm/sn/rw_mmr.h>
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void sn2_ptc_deadlock_recovery(volatile unsigned long *, unsigned long data0,
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volatile unsigned long *, unsigned long data1);
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static __cacheline_aligned DEFINE_SPINLOCK(sn2_global_ptc_lock);
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static unsigned long sn2_ptc_deadlock_count;
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static inline unsigned long wait_piowc(void)
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{
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volatile unsigned long *piows, zeroval;
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unsigned long ws;
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piows = pda->pio_write_status_addr;
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zeroval = pda->pio_write_status_val;
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do {
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cpu_relax();
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} while (((ws = *piows) & SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK) != zeroval);
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return ws;
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}
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void sn_tlb_migrate_finish(struct mm_struct *mm)
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{
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if (mm == current->mm)
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flush_tlb_mm(mm);
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}
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/**
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* sn2_global_tlb_purge - globally purge translation cache of virtual address range
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* @start: start of virtual address range
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* @end: end of virtual address range
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* @nbits: specifies number of bytes to purge per instruction (num = 1<<(nbits & 0xfc))
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*
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* Purges the translation caches of all processors of the given virtual address
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* range.
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*
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* Note:
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* - cpu_vm_mask is a bit mask that indicates which cpus have loaded the context.
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* - cpu_vm_mask is converted into a nodemask of the nodes containing the
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* cpus in cpu_vm_mask.
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* - if only one bit is set in cpu_vm_mask & it is the current cpu,
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* then only the local TLB needs to be flushed. This flushing can be done
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* using ptc.l. This is the common case & avoids the global spinlock.
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* - if multiple cpus have loaded the context, then flushing has to be
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* done with ptc.g/MMRs under protection of the global ptc_lock.
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*/
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void
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sn2_global_tlb_purge(unsigned long start, unsigned long end,
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unsigned long nbits)
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{
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int i, shub1, cnode, mynasid, cpu, lcpu = 0, nasid, flushed = 0;
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volatile unsigned long *ptc0, *ptc1;
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unsigned long flags = 0, data0 = 0, data1 = 0;
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struct mm_struct *mm = current->active_mm;
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short nasids[MAX_NUMNODES], nix;
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nodemask_t nodes_flushed;
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nodes_clear(nodes_flushed);
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i = 0;
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for_each_cpu_mask(cpu, mm->cpu_vm_mask) {
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cnode = cpu_to_node(cpu);
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node_set(cnode, nodes_flushed);
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lcpu = cpu;
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i++;
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}
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preempt_disable();
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if (likely(i == 1 && lcpu == smp_processor_id())) {
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do {
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ia64_ptcl(start, nbits << 2);
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start += (1UL << nbits);
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} while (start < end);
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ia64_srlz_i();
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preempt_enable();
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return;
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}
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if (atomic_read(&mm->mm_users) == 1) {
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flush_tlb_mm(mm);
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preempt_enable();
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return;
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}
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nix = 0;
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for_each_node_mask(cnode, nodes_flushed)
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nasids[nix++] = cnodeid_to_nasid(cnode);
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shub1 = is_shub1();
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if (shub1) {
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data0 = (1UL << SH1_PTC_0_A_SHFT) |
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(nbits << SH1_PTC_0_PS_SHFT) |
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((ia64_get_rr(start) >> 8) << SH1_PTC_0_RID_SHFT) |
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(1UL << SH1_PTC_0_START_SHFT);
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ptc0 = (long *)GLOBAL_MMR_PHYS_ADDR(0, SH1_PTC_0);
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ptc1 = (long *)GLOBAL_MMR_PHYS_ADDR(0, SH1_PTC_1);
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} else {
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data0 = (1UL << SH2_PTC_A_SHFT) |
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(nbits << SH2_PTC_PS_SHFT) |
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(1UL << SH2_PTC_START_SHFT);
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ptc0 = (long *)GLOBAL_MMR_PHYS_ADDR(0, SH2_PTC +
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((ia64_get_rr(start) >> 8) << SH2_PTC_RID_SHFT) );
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ptc1 = NULL;
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}
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mynasid = get_nasid();
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spin_lock_irqsave(&sn2_global_ptc_lock, flags);
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do {
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if (shub1)
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data1 = start | (1UL << SH1_PTC_1_START_SHFT);
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else
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data0 = (data0 & ~SH2_PTC_ADDR_MASK) | (start & SH2_PTC_ADDR_MASK);
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for (i = 0; i < nix; i++) {
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nasid = nasids[i];
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if (unlikely(nasid == mynasid)) {
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ia64_ptcga(start, nbits << 2);
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ia64_srlz_i();
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} else {
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ptc0 = CHANGE_NASID(nasid, ptc0);
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if (ptc1)
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ptc1 = CHANGE_NASID(nasid, ptc1);
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pio_atomic_phys_write_mmrs(ptc0, data0, ptc1,
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data1);
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flushed = 1;
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}
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}
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if (flushed
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&& (wait_piowc() &
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SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_MASK)) {
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sn2_ptc_deadlock_recovery(ptc0, data0, ptc1, data1);
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}
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start += (1UL << nbits);
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} while (start < end);
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spin_unlock_irqrestore(&sn2_global_ptc_lock, flags);
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preempt_enable();
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}
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/*
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* sn2_ptc_deadlock_recovery
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*
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* Recover from PTC deadlocks conditions. Recovery requires stepping thru each
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* TLB flush transaction. The recovery sequence is somewhat tricky & is
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* coded in assembly language.
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*/
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void sn2_ptc_deadlock_recovery(volatile unsigned long *ptc0, unsigned long data0,
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volatile unsigned long *ptc1, unsigned long data1)
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{
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extern void sn2_ptc_deadlock_recovery_core(volatile unsigned long *, unsigned long,
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volatile unsigned long *, unsigned long, volatile unsigned long *, unsigned long);
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int cnode, mycnode, nasid;
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volatile unsigned long *piows;
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volatile unsigned long zeroval;
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sn2_ptc_deadlock_count++;
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piows = pda->pio_write_status_addr;
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zeroval = pda->pio_write_status_val;
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mycnode = numa_node_id();
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for_each_online_node(cnode) {
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if (is_headless_node(cnode) || cnode == mycnode)
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continue;
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nasid = cnodeid_to_nasid(cnode);
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ptc0 = CHANGE_NASID(nasid, ptc0);
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if (ptc1)
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ptc1 = CHANGE_NASID(nasid, ptc1);
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sn2_ptc_deadlock_recovery_core(ptc0, data0, ptc1, data1, piows, zeroval);
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}
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}
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/**
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* sn_send_IPI_phys - send an IPI to a Nasid and slice
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* @nasid: nasid to receive the interrupt (may be outside partition)
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* @physid: physical cpuid to receive the interrupt.
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* @vector: command to send
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* @delivery_mode: delivery mechanism
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*
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* Sends an IPI (interprocessor interrupt) to the processor specified by
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* @physid
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*
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* @delivery_mode can be one of the following
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*
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* %IA64_IPI_DM_INT - pend an interrupt
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* %IA64_IPI_DM_PMI - pend a PMI
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* %IA64_IPI_DM_NMI - pend an NMI
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* %IA64_IPI_DM_INIT - pend an INIT interrupt
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*/
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void sn_send_IPI_phys(int nasid, long physid, int vector, int delivery_mode)
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{
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long val;
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unsigned long flags = 0;
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volatile long *p;
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p = (long *)GLOBAL_MMR_PHYS_ADDR(nasid, SH_IPI_INT);
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val = (1UL << SH_IPI_INT_SEND_SHFT) |
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(physid << SH_IPI_INT_PID_SHFT) |
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((long)delivery_mode << SH_IPI_INT_TYPE_SHFT) |
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((long)vector << SH_IPI_INT_IDX_SHFT) |
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(0x000feeUL << SH_IPI_INT_BASE_SHFT);
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mb();
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if (enable_shub_wars_1_1()) {
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spin_lock_irqsave(&sn2_global_ptc_lock, flags);
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}
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pio_phys_write_mmr(p, val);
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if (enable_shub_wars_1_1()) {
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wait_piowc();
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spin_unlock_irqrestore(&sn2_global_ptc_lock, flags);
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}
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}
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EXPORT_SYMBOL(sn_send_IPI_phys);
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/**
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* sn2_send_IPI - send an IPI to a processor
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* @cpuid: target of the IPI
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* @vector: command to send
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* @delivery_mode: delivery mechanism
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* @redirect: redirect the IPI?
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*
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* Sends an IPI (InterProcessor Interrupt) to the processor specified by
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* @cpuid. @vector specifies the command to send, while @delivery_mode can
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* be one of the following
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*
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* %IA64_IPI_DM_INT - pend an interrupt
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* %IA64_IPI_DM_PMI - pend a PMI
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* %IA64_IPI_DM_NMI - pend an NMI
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* %IA64_IPI_DM_INIT - pend an INIT interrupt
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*/
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void sn2_send_IPI(int cpuid, int vector, int delivery_mode, int redirect)
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{
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long physid;
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int nasid;
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physid = cpu_physical_id(cpuid);
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nasid = cpuid_to_nasid(cpuid);
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/* the following is used only when starting cpus at boot time */
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if (unlikely(nasid == -1))
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ia64_sn_get_sapic_info(physid, &nasid, NULL, NULL);
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sn_send_IPI_phys(nasid, physid, vector, delivery_mode);
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}
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