377 lines
9.3 KiB
C
377 lines
9.3 KiB
C
/*
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* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
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* Copyright (C) 1997, 2001 Ralf Baechle (ralf@gnu.org)
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* Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#include <linux/init.h>
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#include <asm/mmu_context.h>
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#include <asm/bootinfo.h>
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#include <asm/cpu.h>
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extern void build_tlb_refill_handler(void);
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#define UNIQUE_ENTRYHI(idx) (CKSEG0 + ((idx) << (PAGE_SHIFT + 1)))
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/* Dump the current entry* and pagemask registers */
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static inline void dump_cur_tlb_regs(void)
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{
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unsigned int entryhihi, entryhilo, entrylo0hi, entrylo0lo, entrylo1hi;
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unsigned int entrylo1lo, pagemask;
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__asm__ __volatile__ (
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".set push \n"
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".set noreorder \n"
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".set mips64 \n"
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".set noat \n"
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" tlbr \n"
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" dmfc0 $1, $10 \n"
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" dsrl32 %0, $1, 0 \n"
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" sll %1, $1, 0 \n"
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" dmfc0 $1, $2 \n"
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" dsrl32 %2, $1, 0 \n"
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" sll %3, $1, 0 \n"
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" dmfc0 $1, $3 \n"
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" dsrl32 %4, $1, 0 \n"
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" sll %5, $1, 0 \n"
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" mfc0 %6, $5 \n"
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".set pop \n"
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: "=r" (entryhihi), "=r" (entryhilo),
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"=r" (entrylo0hi), "=r" (entrylo0lo),
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"=r" (entrylo1hi), "=r" (entrylo1lo),
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"=r" (pagemask));
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printk("%08X%08X %08X%08X %08X%08X %08X",
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entryhihi, entryhilo,
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entrylo0hi, entrylo0lo,
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entrylo1hi, entrylo1lo,
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pagemask);
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}
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void sb1_dump_tlb(void)
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{
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unsigned long old_ctx;
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unsigned long flags;
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int entry;
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local_irq_save(flags);
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old_ctx = read_c0_entryhi();
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printk("Current TLB registers state:\n"
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" EntryHi EntryLo0 EntryLo1 PageMask Index\n"
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"--------------------------------------------------------------------\n");
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dump_cur_tlb_regs();
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printk(" %08X\n", read_c0_index());
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printk("\n\nFull TLB Dump:\n"
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"Idx EntryHi EntryLo0 EntryLo1 PageMask\n"
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"--------------------------------------------------------------\n");
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for (entry = 0; entry < current_cpu_data.tlbsize; entry++) {
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write_c0_index(entry);
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printk("\n%02i ", entry);
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dump_cur_tlb_regs();
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}
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printk("\n");
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write_c0_entryhi(old_ctx);
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local_irq_restore(flags);
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}
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void local_flush_tlb_all(void)
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{
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unsigned long flags;
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unsigned long old_ctx;
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int entry;
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local_irq_save(flags);
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/* Save old context and create impossible VPN2 value */
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old_ctx = read_c0_entryhi() & ASID_MASK;
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write_c0_entrylo0(0);
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write_c0_entrylo1(0);
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entry = read_c0_wired();
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while (entry < current_cpu_data.tlbsize) {
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write_c0_entryhi(UNIQUE_ENTRYHI(entry));
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write_c0_index(entry);
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tlb_write_indexed();
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entry++;
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}
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write_c0_entryhi(old_ctx);
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local_irq_restore(flags);
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}
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/*
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* Use a bogus region of memory (starting at 0) to sanitize the TLB's.
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* Use increments of the maximum page size (16MB), and check for duplicate
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* entries before doing a given write. Then, when we're safe from collisions
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* with the firmware, go back and give all the entries invalid addresses with
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* the normal flush routine. Wired entries will be killed as well!
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*/
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static void __init sb1_sanitize_tlb(void)
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{
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int entry;
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long addr = 0;
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long inc = 1<<24; /* 16MB */
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/* Save old context and create impossible VPN2 value */
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write_c0_entrylo0(0);
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write_c0_entrylo1(0);
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for (entry = 0; entry < current_cpu_data.tlbsize; entry++) {
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do {
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addr += inc;
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write_c0_entryhi(addr);
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tlb_probe();
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} while ((int)(read_c0_index()) >= 0);
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write_c0_index(entry);
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tlb_write_indexed();
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}
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/* Now that we know we're safe from collisions, we can safely flush
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the TLB with the "normal" routine. */
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local_flush_tlb_all();
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}
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void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
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unsigned long end)
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{
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struct mm_struct *mm = vma->vm_mm;
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unsigned long flags;
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int cpu;
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local_irq_save(flags);
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cpu = smp_processor_id();
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if (cpu_context(cpu, mm) != 0) {
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int size;
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size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
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size = (size + 1) >> 1;
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if (size <= (current_cpu_data.tlbsize/2)) {
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int oldpid = read_c0_entryhi() & ASID_MASK;
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int newpid = cpu_asid(cpu, mm);
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start &= (PAGE_MASK << 1);
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end += ((PAGE_SIZE << 1) - 1);
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end &= (PAGE_MASK << 1);
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while (start < end) {
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int idx;
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write_c0_entryhi(start | newpid);
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start += (PAGE_SIZE << 1);
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tlb_probe();
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idx = read_c0_index();
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write_c0_entrylo0(0);
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write_c0_entrylo1(0);
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write_c0_entryhi(UNIQUE_ENTRYHI(idx));
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if (idx < 0)
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continue;
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tlb_write_indexed();
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}
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write_c0_entryhi(oldpid);
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} else {
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drop_mmu_context(mm, cpu);
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}
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}
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local_irq_restore(flags);
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}
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void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
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{
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unsigned long flags;
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int size;
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size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
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size = (size + 1) >> 1;
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local_irq_save(flags);
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if (size <= (current_cpu_data.tlbsize/2)) {
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int pid = read_c0_entryhi();
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start &= (PAGE_MASK << 1);
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end += ((PAGE_SIZE << 1) - 1);
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end &= (PAGE_MASK << 1);
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while (start < end) {
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int idx;
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write_c0_entryhi(start);
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start += (PAGE_SIZE << 1);
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tlb_probe();
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idx = read_c0_index();
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write_c0_entrylo0(0);
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write_c0_entrylo1(0);
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write_c0_entryhi(UNIQUE_ENTRYHI(idx));
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if (idx < 0)
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continue;
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tlb_write_indexed();
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}
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write_c0_entryhi(pid);
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} else {
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local_flush_tlb_all();
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}
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local_irq_restore(flags);
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}
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void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
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{
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unsigned long flags;
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int cpu = smp_processor_id();
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local_irq_save(flags);
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if (cpu_context(cpu, vma->vm_mm) != 0) {
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int oldpid, newpid, idx;
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newpid = cpu_asid(cpu, vma->vm_mm);
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page &= (PAGE_MASK << 1);
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oldpid = read_c0_entryhi() & ASID_MASK;
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write_c0_entryhi(page | newpid);
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tlb_probe();
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idx = read_c0_index();
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write_c0_entrylo0(0);
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write_c0_entrylo1(0);
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if (idx < 0)
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goto finish;
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/* Make sure all entries differ. */
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write_c0_entryhi(UNIQUE_ENTRYHI(idx));
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tlb_write_indexed();
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finish:
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write_c0_entryhi(oldpid);
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}
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local_irq_restore(flags);
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}
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/*
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* Remove one kernel space TLB entry. This entry is assumed to be marked
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* global so we don't do the ASID thing.
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*/
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void local_flush_tlb_one(unsigned long page)
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{
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unsigned long flags;
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int oldpid, idx;
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page &= (PAGE_MASK << 1);
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oldpid = read_c0_entryhi() & ASID_MASK;
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local_irq_save(flags);
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write_c0_entryhi(page);
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tlb_probe();
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idx = read_c0_index();
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if (idx >= 0) {
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/* Make sure all entries differ. */
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write_c0_entryhi(UNIQUE_ENTRYHI(idx));
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write_c0_entrylo0(0);
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write_c0_entrylo1(0);
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tlb_write_indexed();
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}
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write_c0_entryhi(oldpid);
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local_irq_restore(flags);
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}
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/* All entries common to a mm share an asid. To effectively flush
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these entries, we just bump the asid. */
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void local_flush_tlb_mm(struct mm_struct *mm)
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{
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int cpu;
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preempt_disable();
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cpu = smp_processor_id();
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if (cpu_context(cpu, mm) != 0) {
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drop_mmu_context(mm, cpu);
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}
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preempt_enable();
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}
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/* Stolen from mips32 routines */
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void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
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{
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unsigned long flags;
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pgd_t *pgdp;
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pmd_t *pmdp;
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pte_t *ptep;
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int idx, pid;
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/*
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* Handle debugger faulting in for debugee.
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*/
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if (current->active_mm != vma->vm_mm)
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return;
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local_irq_save(flags);
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pid = read_c0_entryhi() & ASID_MASK;
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address &= (PAGE_MASK << 1);
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write_c0_entryhi(address | (pid));
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pgdp = pgd_offset(vma->vm_mm, address);
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tlb_probe();
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pmdp = pmd_offset(pgdp, address);
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idx = read_c0_index();
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ptep = pte_offset_map(pmdp, address);
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write_c0_entrylo0(pte_val(*ptep++) >> 6);
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write_c0_entrylo1(pte_val(*ptep) >> 6);
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if (idx < 0) {
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tlb_write_random();
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} else {
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tlb_write_indexed();
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}
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local_irq_restore(flags);
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}
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void __init add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
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unsigned long entryhi, unsigned long pagemask)
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{
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unsigned long flags;
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unsigned long wired;
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unsigned long old_pagemask;
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unsigned long old_ctx;
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local_irq_save(flags);
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old_ctx = read_c0_entryhi() & 0xff;
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old_pagemask = read_c0_pagemask();
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wired = read_c0_wired();
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write_c0_wired(wired + 1);
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write_c0_index(wired);
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write_c0_pagemask(pagemask);
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write_c0_entryhi(entryhi);
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write_c0_entrylo0(entrylo0);
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write_c0_entrylo1(entrylo1);
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tlb_write_indexed();
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write_c0_entryhi(old_ctx);
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write_c0_pagemask(old_pagemask);
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local_flush_tlb_all();
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local_irq_restore(flags);
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}
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/*
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* This is called from loadmmu.c. We have to set up all the
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* memory management function pointers, as well as initialize
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* the caches and tlbs
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*/
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void tlb_init(void)
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{
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write_c0_pagemask(PM_DEFAULT_MASK);
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write_c0_wired(0);
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/*
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* We don't know what state the firmware left the TLB's in, so this is
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* the ultra-conservative way to flush the TLB's and avoid machine
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* check exceptions due to duplicate TLB entries
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*/
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sb1_sanitize_tlb();
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build_tlb_refill_handler();
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}
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