original_kernel/arch/mips/mm
Thomas Bogendoerfer 14defd90f5 [MIPS] Fix 32bit kernels on R4k with 128 byte cache line size
The generated copy_page for R4k CPU with a 128 byte cache line size used
Create Dirty Exclusive cache line operations even if only part of the
cache line was filled.  This change avoids generating cache operations,
if only part of the cache line size is copied in one loop. It also
increases the maxmimum loop size, because the generated code even fits
into the available space for r4k CPUs with 128 byte cache line size.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-07-08 19:33:46 +01:00
..
Makefile
c-r3k.c [MIPS] Atlas, decstation: Fix section mismatches triggered by defconfigs 2008-07-08 19:33:46 +01:00
c-r4k.c [MIPS] Fix buggy use of kmap_coherent. 2008-06-16 15:14:48 +01:00
c-tx39.c
cache.c
cerr-sb1.c
cex-gen.S
cex-sb1.S
dma-default.c
extable.c
fault.c
highmem.c [MIPS] unexport __kmap_atomic_to_page 2008-05-12 16:46:51 +01:00
init.c [MIPS] Export empty_zero_page for sake of the ext4 module. 2008-06-16 15:14:46 +01:00
ioremap.c
page.c [MIPS] Fix 32bit kernels on R4k with 128 byte cache line size 2008-07-08 19:33:46 +01:00
pgtable-32.c
pgtable-64.c
pgtable.c
sc-ip22.c
sc-mips.c
sc-r5k.c
sc-rm7k.c [MIPS] Atlas, decstation: Fix section mismatches triggered by defconfigs 2008-07-08 19:33:46 +01:00
tlb-r3k.c
tlb-r4k.c
tlb-r8k.c
tlbex-fault.S
tlbex.c [MIPS] R4700: Fix build_tlb_probe_entry 2008-06-05 18:13:14 +01:00
uasm.c
uasm.h