273 lines
6.1 KiB
C
273 lines
6.1 KiB
C
/*
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* External interrupt handling for AT32AP CPUs
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*
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* Copyright (C) 2006 Atmel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/platform_device.h>
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#include <linux/random.h>
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#include <linux/slab.h>
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#include <asm/io.h>
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/* EIC register offsets */
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#define EIC_IER 0x0000
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#define EIC_IDR 0x0004
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#define EIC_IMR 0x0008
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#define EIC_ISR 0x000c
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#define EIC_ICR 0x0010
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#define EIC_MODE 0x0014
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#define EIC_EDGE 0x0018
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#define EIC_LEVEL 0x001c
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#define EIC_NMIC 0x0024
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/* Bitfields in NMIC */
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#define EIC_NMIC_ENABLE (1 << 0)
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/* Bit manipulation macros */
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#define EIC_BIT(name) \
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(1 << EIC_##name##_OFFSET)
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#define EIC_BF(name,value) \
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(((value) & ((1 << EIC_##name##_SIZE) - 1)) \
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<< EIC_##name##_OFFSET)
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#define EIC_BFEXT(name,value) \
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(((value) >> EIC_##name##_OFFSET) \
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& ((1 << EIC_##name##_SIZE) - 1))
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#define EIC_BFINS(name,value,old) \
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(((old) & ~(((1 << EIC_##name##_SIZE) - 1) \
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<< EIC_##name##_OFFSET)) \
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| EIC_BF(name,value))
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/* Register access macros */
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#define eic_readl(port,reg) \
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__raw_readl((port)->regs + EIC_##reg)
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#define eic_writel(port,reg,value) \
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__raw_writel((value), (port)->regs + EIC_##reg)
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struct eic {
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void __iomem *regs;
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struct irq_chip *chip;
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unsigned int first_irq;
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};
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static struct eic *nmi_eic;
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static bool nmi_enabled;
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static void eic_ack_irq(struct irq_data *d)
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{
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struct eic *eic = irq_data_get_irq_chip_data(d);
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eic_writel(eic, ICR, 1 << (d->irq - eic->first_irq));
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}
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static void eic_mask_irq(struct irq_data *d)
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{
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struct eic *eic = irq_data_get_irq_chip_data(d);
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eic_writel(eic, IDR, 1 << (d->irq - eic->first_irq));
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}
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static void eic_mask_ack_irq(struct irq_data *d)
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{
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struct eic *eic = irq_data_get_irq_chip_data(d);
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eic_writel(eic, ICR, 1 << (d->irq - eic->first_irq));
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eic_writel(eic, IDR, 1 << (d->irq - eic->first_irq));
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}
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static void eic_unmask_irq(struct irq_data *d)
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{
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struct eic *eic = irq_data_get_irq_chip_data(d);
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eic_writel(eic, IER, 1 << (d->irq - eic->first_irq));
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}
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static int eic_set_irq_type(struct irq_data *d, unsigned int flow_type)
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{
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struct eic *eic = irq_data_get_irq_chip_data(d);
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unsigned int irq = d->irq;
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unsigned int i = irq - eic->first_irq;
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u32 mode, edge, level;
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flow_type &= IRQ_TYPE_SENSE_MASK;
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if (flow_type == IRQ_TYPE_NONE)
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flow_type = IRQ_TYPE_LEVEL_LOW;
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mode = eic_readl(eic, MODE);
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edge = eic_readl(eic, EDGE);
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level = eic_readl(eic, LEVEL);
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switch (flow_type) {
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case IRQ_TYPE_LEVEL_LOW:
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mode |= 1 << i;
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level &= ~(1 << i);
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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mode |= 1 << i;
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level |= 1 << i;
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break;
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case IRQ_TYPE_EDGE_RISING:
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mode &= ~(1 << i);
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edge |= 1 << i;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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mode &= ~(1 << i);
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edge &= ~(1 << i);
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break;
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default:
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return -EINVAL;
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}
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eic_writel(eic, MODE, mode);
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eic_writel(eic, EDGE, edge);
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eic_writel(eic, LEVEL, level);
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irqd_set_trigger_type(d, flow_type);
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if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
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__irq_set_handler_locked(irq, handle_level_irq);
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else
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__irq_set_handler_locked(irq, handle_edge_irq);
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return IRQ_SET_MASK_OK_NOCOPY;
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}
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static struct irq_chip eic_chip = {
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.name = "eic",
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.irq_ack = eic_ack_irq,
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.irq_mask = eic_mask_irq,
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.irq_mask_ack = eic_mask_ack_irq,
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.irq_unmask = eic_unmask_irq,
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.irq_set_type = eic_set_irq_type,
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};
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static void demux_eic_irq(unsigned int irq, struct irq_desc *desc)
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{
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struct eic *eic = irq_desc_get_handler_data(desc);
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unsigned long status, pending;
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unsigned int i;
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status = eic_readl(eic, ISR);
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pending = status & eic_readl(eic, IMR);
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while (pending) {
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i = fls(pending) - 1;
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pending &= ~(1 << i);
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generic_handle_irq(i + eic->first_irq);
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}
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}
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int nmi_enable(void)
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{
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nmi_enabled = true;
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if (nmi_eic)
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eic_writel(nmi_eic, NMIC, EIC_NMIC_ENABLE);
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return 0;
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}
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void nmi_disable(void)
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{
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if (nmi_eic)
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eic_writel(nmi_eic, NMIC, 0);
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nmi_enabled = false;
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}
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static int __init eic_probe(struct platform_device *pdev)
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{
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struct eic *eic;
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struct resource *regs;
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unsigned int i;
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unsigned int nr_of_irqs;
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unsigned int int_irq;
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int ret;
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u32 pattern;
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regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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int_irq = platform_get_irq(pdev, 0);
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if (!regs || (int)int_irq <= 0) {
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dev_dbg(&pdev->dev, "missing regs and/or irq resource\n");
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return -ENXIO;
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}
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ret = -ENOMEM;
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eic = kzalloc(sizeof(struct eic), GFP_KERNEL);
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if (!eic) {
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dev_dbg(&pdev->dev, "no memory for eic structure\n");
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goto err_kzalloc;
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}
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eic->first_irq = EIM_IRQ_BASE + 32 * pdev->id;
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eic->regs = ioremap(regs->start, regs->end - regs->start + 1);
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if (!eic->regs) {
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dev_dbg(&pdev->dev, "failed to map regs\n");
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goto err_ioremap;
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}
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/*
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* Find out how many interrupt lines that are actually
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* implemented in hardware.
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*/
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eic_writel(eic, IDR, ~0UL);
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eic_writel(eic, MODE, ~0UL);
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pattern = eic_readl(eic, MODE);
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nr_of_irqs = fls(pattern);
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/* Trigger on low level unless overridden by driver */
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eic_writel(eic, EDGE, 0UL);
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eic_writel(eic, LEVEL, 0UL);
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eic->chip = &eic_chip;
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for (i = 0; i < nr_of_irqs; i++) {
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irq_set_chip_and_handler(eic->first_irq + i, &eic_chip,
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handle_level_irq);
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irq_set_chip_data(eic->first_irq + i, eic);
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}
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irq_set_chained_handler(int_irq, demux_eic_irq);
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irq_set_handler_data(int_irq, eic);
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if (pdev->id == 0) {
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nmi_eic = eic;
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if (nmi_enabled)
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/*
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* Someone tried to enable NMI before we were
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* ready. Do it now.
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*/
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nmi_enable();
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}
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dev_info(&pdev->dev,
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"External Interrupt Controller at 0x%p, IRQ %u\n",
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eic->regs, int_irq);
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dev_info(&pdev->dev,
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"Handling %u external IRQs, starting with IRQ %u\n",
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nr_of_irqs, eic->first_irq);
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return 0;
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err_ioremap:
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kfree(eic);
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err_kzalloc:
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return ret;
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}
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static struct platform_driver eic_driver = {
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.driver = {
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.name = "at32_eic",
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},
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};
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static int __init eic_init(void)
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{
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return platform_driver_probe(&eic_driver, eic_probe);
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}
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arch_initcall(eic_init);
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