125 lines
3.5 KiB
ArmAsm
125 lines
3.5 KiB
ArmAsm
/*
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* arch/arm/plat-omap/include/mach/entry-macro.S
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*
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* Low-level IRQ helper macros for OMAP-based platforms
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*
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* Copyright (C) 2009 Texas Instruments
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* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <mach/hardware.h>
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#include <mach/io.h>
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#include <mach/irqs.h>
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#include <asm/hardware/gic.h>
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#include <plat/omap24xx.h>
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#include <plat/omap34xx.h>
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/* REVISIT: This should be set dynamically if CONFIG_MULTI_OMAP2 is selected */
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#if defined(CONFIG_ARCH_OMAP2420) || defined(CONFIG_ARCH_OMAP2430)
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#define OMAP2_VA_IC_BASE OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
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#elif defined(CONFIG_ARCH_OMAP34XX)
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#define OMAP2_VA_IC_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
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#endif
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#if defined(CONFIG_ARCH_OMAP4)
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#include <plat/omap44xx.h>
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#endif
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#define INTCPS_SIR_IRQ_OFFSET 0x0040 /* Active interrupt offset */
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#define ACTIVEIRQ_MASK 0x7f /* Active interrupt bits */
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.macro disable_fiq
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.endm
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.macro get_irqnr_preamble, base, tmp
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.endm
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.macro arch_ret_to_user, tmp1, tmp2
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.endm
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#ifndef CONFIG_ARCH_OMAP4
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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ldr \base, =OMAP2_VA_IC_BASE
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ldr \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
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cmp \irqnr, #0x0
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bne 2222f
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ldr \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
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cmp \irqnr, #0x0
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bne 2222f
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ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
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cmp \irqnr, #0x0
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2222:
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ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
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and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
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.endm
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#else
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#define OMAP44XX_VA_GIC_CPU_BASE OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)
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/*
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* The interrupt numbering scheme is defined in the
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* interrupt controller spec. To wit:
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*
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* Interrupts 0-15 are IPI
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* 16-28 are reserved
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* 29-31 are local. We allow 30 to be used for the watchdog.
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* 32-1020 are global
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* 1021-1022 are reserved
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* 1023 is "spurious" (no interrupt)
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*
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* For now, we ignore all local interrupts so only return an
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* interrupt if it's between 30 and 1020. The test_for_ipi
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* routine below will pick up on IPIs.
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* A simple read from the controller will tell us the number
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* of the highest priority enabled interrupt.
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* We then just need to check whether it is in the
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* valid range for an IRQ (30-1020 inclusive).
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*/
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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ldr \base, =OMAP44XX_VA_GIC_CPU_BASE
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ldr \irqstat, [\base, #GIC_CPU_INTACK]
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ldr \tmp, =1021
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bic \irqnr, \irqstat, #0x1c00
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cmp \irqnr, #29
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cmpcc \irqnr, \irqnr
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cmpne \irqnr, \tmp
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cmpcs \irqnr, \irqnr
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.endm
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/* We assume that irqstat (the raw value of the IRQ acknowledge
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* register) is preserved from the macro above.
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* If there is an IPI, we immediately signal end of interrupt
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* on the controller, since this requires the original irqstat
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* value which we won't easily be able to recreate later.
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*/
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.macro test_for_ipi, irqnr, irqstat, base, tmp
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bic \irqnr, \irqstat, #0x1c00
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cmp \irqnr, #16
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it cc
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strcc \irqstat, [\base, #GIC_CPU_EOI]
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it cs
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cmpcs \irqnr, \irqnr
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.endm
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/* As above, this assumes that irqstat and base are preserved */
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.macro test_for_ltirq, irqnr, irqstat, base, tmp
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bic \irqnr, \irqstat, #0x1c00
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mov \tmp, #0
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cmp \irqnr, #29
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itt eq
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moveq \tmp, #1
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streq \irqstat, [\base, #GIC_CPU_EOI]
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cmp \tmp, #0
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.endm
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#endif
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.macro irq_prio_table
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.endm
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