Dan Williams 2aec048cdc ioat3: hardware version 3.2 register / descriptor definitions ... ioat3.2 adds raid5 and raid6 offload capabilities. Signed-off-by: Tom Picard <tom.s.picard@intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>		2009-09-08 17:42:54 -07:00
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Makefile	ioat2,3: convert to a true ring buffer	2009-09-08 17:29:55 -07:00
dca.c	ioat: ___devinit annotate the initialization paths	2009-09-08 17:30:24 -07:00
dma.c	ioat: switch watchdog and reset handler from workqueue to timer	2009-09-08 17:30:24 -07:00
dma.h	ioat3: hardware version 3.2 register / descriptor definitions	2009-09-08 17:42:54 -07:00
dma_v2.c	ioat2+: add fence support	2009-09-08 17:42:53 -07:00
dma_v2.h	ioat3: hardware version 3.2 register / descriptor definitions	2009-09-08 17:42:54 -07:00
hw.h	ioat3: hardware version 3.2 register / descriptor definitions	2009-09-08 17:42:54 -07:00
pci.c	ioat2,3: convert to a true ring buffer	2009-09-08 17:29:55 -07:00
registers.h	ioat3: hardware version 3.2 register / descriptor definitions	2009-09-08 17:42:54 -07:00