93 lines
2.8 KiB
Plaintext
93 lines
2.8 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0
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if CPU_CAVIUM_OCTEON
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config CAVIUM_CN63XXP1
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bool "Enable CN63XXP1 errata workarounds"
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default "n"
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help
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The CN63XXP1 chip requires build time workarounds to
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function reliably, select this option to enable them. These
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workarounds will cause a slight decrease in performance on
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non-CN63XXP1 hardware, so it is recommended to select "n"
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unless it is known the workarounds are needed.
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config CAVIUM_OCTEON_CVMSEG_SIZE
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int "Number of L1 cache lines reserved for CVMSEG memory"
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range 0 54
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default 0 if !CAVIUM_OCTEON_SOC
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default 1 if CAVIUM_OCTEON_SOC
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help
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CVMSEG LM is a segment that accesses portions of the dcache as a
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local memory; the larger CVMSEG is, the smaller the cache is.
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This selects the size of CVMSEG LM, which is in cache blocks. The
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legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is
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between zero and 6192 bytes).
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endif # CPU_CAVIUM_OCTEON
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if CAVIUM_OCTEON_SOC
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config CAVIUM_OCTEON_LOCK_L2
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bool "Lock often used kernel code in the L2"
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default "y"
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help
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Enable locking parts of the kernel into the L2 cache.
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config CAVIUM_OCTEON_LOCK_L2_TLB
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bool "Lock the TLB handler in L2"
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depends on CAVIUM_OCTEON_LOCK_L2
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default "y"
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help
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Lock the low level TLB fast path into L2.
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config CAVIUM_OCTEON_LOCK_L2_EXCEPTION
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bool "Lock the exception handler in L2"
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depends on CAVIUM_OCTEON_LOCK_L2
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default "y"
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help
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Lock the low level exception handler into L2.
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config CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT
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bool "Lock the interrupt handler in L2"
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depends on CAVIUM_OCTEON_LOCK_L2
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default "y"
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help
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Lock the low level interrupt handler into L2.
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config CAVIUM_OCTEON_LOCK_L2_INTERRUPT
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bool "Lock the 2nd level interrupt handler in L2"
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depends on CAVIUM_OCTEON_LOCK_L2
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default "y"
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help
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Lock the 2nd level interrupt handler in L2.
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config CAVIUM_OCTEON_LOCK_L2_MEMCPY
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bool "Lock memcpy() in L2"
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depends on CAVIUM_OCTEON_LOCK_L2
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default "y"
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help
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Lock the kernel's implementation of memcpy() into L2.
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config CAVIUM_RESERVE32
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int "Memory to reserve for user processes shared region (MB)"
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range 0 1536
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default "0"
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help
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Reserve a shared memory region for user processes to use for hardware
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memory buffers. This is required for 32bit applications to be able to
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send and receive packets directly. Applications access this memory by
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memory mapping /dev/mem for the addresses in /proc/octeon_info. For
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optimal performance with HugeTLBs, keep this size an even number of
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megabytes.
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config OCTEON_ILM
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tristate "Module to measure interrupt latency using Octeon CIU Timer"
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help
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This driver is a module to measure interrupt latency using the
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the CIU Timers on Octeon.
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To compile this driver as a module, choose M here. The module
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will be called octeon-ilm
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endif # CAVIUM_OCTEON_SOC
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