15 lines
689 B
C
15 lines
689 B
C
#ifndef _SPARC64_DCR_H
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#define _SPARC64_DCR_H
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/* UltraSparc-III/III+ Dispatch Control Register, ASR 0x12 */
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#define DCR_DPE 0x0000000000001000 /* III+: D$ Parity Error Enable */
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#define DCR_OBS 0x0000000000000fc0 /* Observability Bus Controls */
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#define DCR_BPE 0x0000000000000020 /* Branch Predict Enable */
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#define DCR_RPE 0x0000000000000010 /* Return Address Prediction Enable */
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#define DCR_SI 0x0000000000000008 /* Single Instruction Disable */
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#define DCR_IPE 0x0000000000000004 /* III+: I$ Parity Error Enable */
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#define DCR_IFPOE 0x0000000000000002 /* IRQ FP Operation Enable */
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#define DCR_MS 0x0000000000000001 /* Multi-Scalar dispatch */
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#endif /* _SPARC64_DCR_H */
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