56 lines
2.1 KiB
C
56 lines
2.1 KiB
C
#ifndef __PARISC_LDCW_H
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#define __PARISC_LDCW_H
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#ifndef CONFIG_PA20
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/* Because kmalloc only guarantees 8-byte alignment for kmalloc'd data,
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and GCC only guarantees 8-byte alignment for stack locals, we can't
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be assured of 16-byte alignment for atomic lock data even if we
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specify "__attribute ((aligned(16)))" in the type declaration. So,
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we use a struct containing an array of four ints for the atomic lock
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type and dynamically select the 16-byte aligned int from the array
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for the semaphore. */
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#define __PA_LDCW_ALIGNMENT 16
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#define __ldcw_align(a) ({ \
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unsigned long __ret = (unsigned long) &(a)->lock[0]; \
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__ret = (__ret + __PA_LDCW_ALIGNMENT - 1) \
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& ~(__PA_LDCW_ALIGNMENT - 1); \
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(volatile unsigned int *) __ret; \
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})
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#define __LDCW "ldcw"
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#else /*CONFIG_PA20*/
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/* From: "Jim Hull" <jim.hull of hp.com>
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I've attached a summary of the change, but basically, for PA 2.0, as
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long as the ",CO" (coherent operation) completer is specified, then the
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16-byte alignment requirement for ldcw and ldcd is relaxed, and instead
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they only require "natural" alignment (4-byte for ldcw, 8-byte for
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ldcd). */
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#define __PA_LDCW_ALIGNMENT 4
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#define __ldcw_align(a) (&(a)->slock)
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#define __LDCW "ldcw,co"
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#endif /*!CONFIG_PA20*/
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/* LDCW, the only atomic read-write operation PA-RISC has. *sigh*.
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We don't explicitly expose that "*a" may be written as reload
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fails to find a register in class R1_REGS when "a" needs to be
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reloaded when generating 64-bit PIC code. Instead, we clobber
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memory to indicate to the compiler that the assembly code reads
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or writes to items other than those listed in the input and output
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operands. This may pessimize the code somewhat but __ldcw is
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usually used within code blocks surrounded by memory barriors. */
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#define __ldcw(a) ({ \
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unsigned __ret; \
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__asm__ __volatile__(__LDCW " 0(%1),%0" \
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: "=r" (__ret) : "r" (a) : "memory"); \
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__ret; \
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})
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#ifdef CONFIG_SMP
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# define __lock_aligned __attribute__((__section__(".data..lock_aligned")))
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#endif
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#endif /* __PARISC_LDCW_H */
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