259 lines
7.8 KiB
C
259 lines
7.8 KiB
C
/*
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* Copyright 2010 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*/
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/*
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* @file
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* Global header file.
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* This header file specifies defines for TILEPro.
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*/
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#ifndef __ARCH_CHIP_H__
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#define __ARCH_CHIP_H__
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/** Specify chip version.
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* When possible, prefer the CHIP_xxx symbols below for future-proofing.
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* This is intended for cross-compiling; native compilation should
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* use the predefined __tile_chip__ symbol.
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*/
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#define TILE_CHIP 1
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/** Specify chip revision.
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* This provides for the case of a respin of a particular chip type;
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* the normal value for this symbol is "0".
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* This is intended for cross-compiling; native compilation should
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* use the predefined __tile_chip_rev__ symbol.
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*/
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#define TILE_CHIP_REV 0
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/** The name of this architecture. */
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#define CHIP_ARCH_NAME "tilepro"
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/** The ELF e_machine type for binaries for this chip. */
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#define CHIP_ELF_TYPE() EM_TILEPRO
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/** The alternate ELF e_machine type for binaries for this chip. */
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#define CHIP_COMPAT_ELF_TYPE() 0x2507
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/** What is the native word size of the machine? */
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#define CHIP_WORD_SIZE() 32
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/** How many bits of a virtual address are used. Extra bits must be
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* the sign extension of the low bits.
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*/
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#define CHIP_VA_WIDTH() 32
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/** How many bits are in a physical address? */
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#define CHIP_PA_WIDTH() 36
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/** Size of the L2 cache, in bytes. */
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#define CHIP_L2_CACHE_SIZE() 65536
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/** Log size of an L2 cache line in bytes. */
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#define CHIP_L2_LOG_LINE_SIZE() 6
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/** Size of an L2 cache line, in bytes. */
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#define CHIP_L2_LINE_SIZE() (1 << CHIP_L2_LOG_LINE_SIZE())
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/** Associativity of the L2 cache. */
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#define CHIP_L2_ASSOC() 4
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/** Size of the L1 data cache, in bytes. */
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#define CHIP_L1D_CACHE_SIZE() 8192
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/** Log size of an L1 data cache line in bytes. */
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#define CHIP_L1D_LOG_LINE_SIZE() 4
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/** Size of an L1 data cache line, in bytes. */
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#define CHIP_L1D_LINE_SIZE() (1 << CHIP_L1D_LOG_LINE_SIZE())
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/** Associativity of the L1 data cache. */
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#define CHIP_L1D_ASSOC() 2
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/** Size of the L1 instruction cache, in bytes. */
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#define CHIP_L1I_CACHE_SIZE() 16384
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/** Log size of an L1 instruction cache line in bytes. */
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#define CHIP_L1I_LOG_LINE_SIZE() 6
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/** Size of an L1 instruction cache line, in bytes. */
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#define CHIP_L1I_LINE_SIZE() (1 << CHIP_L1I_LOG_LINE_SIZE())
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/** Associativity of the L1 instruction cache. */
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#define CHIP_L1I_ASSOC() 1
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/** Stride with which flush instructions must be issued. */
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#define CHIP_FLUSH_STRIDE() CHIP_L2_LINE_SIZE()
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/** Stride with which inv instructions must be issued. */
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#define CHIP_INV_STRIDE() CHIP_L2_LINE_SIZE()
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/** Stride with which finv instructions must be issued. */
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#define CHIP_FINV_STRIDE() CHIP_L2_LINE_SIZE()
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/** Can the local cache coherently cache data that is homed elsewhere? */
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#define CHIP_HAS_COHERENT_LOCAL_CACHE() 1
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/** How many simultaneous outstanding victims can the L2 cache have? */
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#define CHIP_MAX_OUTSTANDING_VICTIMS() 4
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/** Does the TLB support the NC and NOALLOC bits? */
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#define CHIP_HAS_NC_AND_NOALLOC_BITS() 1
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/** Does the chip support hash-for-home caching? */
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#define CHIP_HAS_CBOX_HOME_MAP() 1
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/** Number of entries in the chip's home map tables. */
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#define CHIP_CBOX_HOME_MAP_SIZE() 64
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/** Do uncacheable requests miss in the cache regardless of whether
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* there is matching data? */
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#define CHIP_HAS_ENFORCED_UNCACHEABLE_REQUESTS() 1
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/** Does the mf instruction wait for victims? */
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#define CHIP_HAS_MF_WAITS_FOR_VICTIMS() 0
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/** Does the chip have an "inv" instruction that doesn't also flush? */
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#define CHIP_HAS_INV() 1
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/** Does the chip have a "wh64" instruction? */
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#define CHIP_HAS_WH64() 1
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/** Does this chip have a 'dword_align' instruction? */
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#define CHIP_HAS_DWORD_ALIGN() 1
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/** Number of performance counters. */
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#define CHIP_PERFORMANCE_COUNTERS() 4
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/** Does this chip have auxiliary performance counters? */
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#define CHIP_HAS_AUX_PERF_COUNTERS() 1
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/** Is the CBOX_MSR1 SPR supported? */
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#define CHIP_HAS_CBOX_MSR1() 1
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/** Is the TILE_RTF_HWM SPR supported? */
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#define CHIP_HAS_TILE_RTF_HWM() 1
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/** Is the TILE_WRITE_PENDING SPR supported? */
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#define CHIP_HAS_TILE_WRITE_PENDING() 1
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/** Is the PROC_STATUS SPR supported? */
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#define CHIP_HAS_PROC_STATUS_SPR() 1
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/** Is the DSTREAM_PF SPR supported? */
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#define CHIP_HAS_DSTREAM_PF() 0
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/** Log of the number of mshims we have. */
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#define CHIP_LOG_NUM_MSHIMS() 2
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/** Are the bases of the interrupt vector areas fixed? */
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#define CHIP_HAS_FIXED_INTVEC_BASE() 1
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/** Are the interrupt masks split up into 2 SPRs? */
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#define CHIP_HAS_SPLIT_INTR_MASK() 1
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/** Is the cycle count split up into 2 SPRs? */
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#define CHIP_HAS_SPLIT_CYCLE() 1
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/** Does the chip have a static network? */
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#define CHIP_HAS_SN() 1
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/** Does the chip have a static network processor? */
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#define CHIP_HAS_SN_PROC() 0
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/** Size of the L1 static network processor instruction cache, in bytes. */
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/* #define CHIP_L1SNI_CACHE_SIZE() -- does not apply to chip 1 */
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/** Does the chip have DMA support in each tile? */
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#define CHIP_HAS_TILE_DMA() 1
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/** Does the chip have the second revision of the directly accessible
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* dynamic networks? This encapsulates a number of characteristics,
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* including the absence of the catch-all, the absence of inline message
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* tags, the absence of support for network context-switching, and so on.
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*/
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#define CHIP_HAS_REV1_XDN() 0
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/** Does the chip have cmpexch and similar (fetchadd, exch, etc.)? */
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#define CHIP_HAS_CMPEXCH() 0
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/** Does the chip have memory-mapped I/O support? */
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#define CHIP_HAS_MMIO() 0
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/** Does the chip have post-completion interrupts? */
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#define CHIP_HAS_POST_COMPLETION_INTERRUPTS() 0
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/** Does the chip have native single step support? */
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#define CHIP_HAS_SINGLE_STEP() 0
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#ifndef __OPEN_SOURCE__ /* features only relevant to hypervisor-level code */
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/** How many entries are present in the instruction TLB? */
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#define CHIP_ITLB_ENTRIES() 16
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/** How many entries are present in the data TLB? */
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#define CHIP_DTLB_ENTRIES() 16
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/** How many MAF entries does the XAUI shim have? */
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#define CHIP_XAUI_MAF_ENTRIES() 32
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/** Does the memory shim have a source-id table? */
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#define CHIP_HAS_MSHIM_SRCID_TABLE() 0
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/** Does the L1 instruction cache clear on reset? */
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#define CHIP_HAS_L1I_CLEAR_ON_RESET() 1
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/** Does the chip come out of reset with valid coordinates on all tiles?
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* Note that if defined, this also implies that the upper left is 1,1.
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*/
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#define CHIP_HAS_VALID_TILE_COORD_RESET() 1
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/** Does the chip have unified packet formats? */
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#define CHIP_HAS_UNIFIED_PACKET_FORMATS() 1
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/** Does the chip support write reordering? */
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#define CHIP_HAS_WRITE_REORDERING() 1
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/** Does the chip support Y-X routing as well as X-Y? */
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#define CHIP_HAS_Y_X_ROUTING() 1
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/** Is INTCTRL_3 managed with the correct MPL? */
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#define CHIP_HAS_INTCTRL_3_STATUS_FIX() 1
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/** Is it possible to configure the chip to be big-endian? */
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#define CHIP_HAS_BIG_ENDIAN_CONFIG() 1
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/** Is the CACHE_RED_WAY_OVERRIDDEN SPR supported? */
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#define CHIP_HAS_CACHE_RED_WAY_OVERRIDDEN() 1
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/** Is the DIAG_TRACE_WAY SPR supported? */
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#define CHIP_HAS_DIAG_TRACE_WAY() 1
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/** Is the MEM_STRIPE_CONFIG SPR supported? */
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#define CHIP_HAS_MEM_STRIPE_CONFIG() 1
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/** Are the TLB_PERF SPRs supported? */
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#define CHIP_HAS_TLB_PERF() 1
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/** Is the VDN_SNOOP_SHIM_CTL SPR supported? */
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#define CHIP_HAS_VDN_SNOOP_SHIM_CTL() 1
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/** Does the chip support rev1 DMA packets? */
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#define CHIP_HAS_REV1_DMA_PACKETS() 1
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/** Does the chip have an IPI shim? */
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#define CHIP_HAS_IPI() 0
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#endif /* !__OPEN_SOURCE__ */
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#endif /* __ARCH_CHIP_H__ */
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