138 lines
3.6 KiB
C
138 lines
3.6 KiB
C
/*
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* TX3927 setup routines
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* Based on linux/arch/mips/txx9/jmr3927/setup.c
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*
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* Copyright 2001 MontaVista Software Inc.
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* Copyright (C) 2000-2001 Toshiba Corporation
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* Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/delay.h>
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#include <linux/param.h>
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#include <linux/io.h>
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#include <linux/mtd/physmap.h>
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#include <asm/mipsregs.h>
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#include <asm/txx9irq.h>
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#include <asm/txx9tmr.h>
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#include <asm/txx9pio.h>
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#include <asm/txx9/generic.h>
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#include <asm/txx9/tx3927.h>
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void __init tx3927_wdt_init(void)
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{
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txx9_wdt_init(TX3927_TMR_REG(2));
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}
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void __init tx3927_setup(void)
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{
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int i;
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unsigned int conf;
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txx9_reg_res_init(TX3927_REV_PCODE(), TX3927_REG_BASE,
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TX3927_REG_SIZE);
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/* SDRAMC,ROMC are configured by PROM */
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for (i = 0; i < 8; i++) {
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if (!(tx3927_romcptr->cr[i] & 0x8))
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continue; /* disabled */
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txx9_ce_res[i].start = (unsigned long)TX3927_ROMC_BA(i);
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txx9_ce_res[i].end =
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txx9_ce_res[i].start + TX3927_ROMC_SIZE(i) - 1;
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request_resource(&iomem_resource, &txx9_ce_res[i]);
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}
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/* clocks */
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txx9_gbus_clock = txx9_cpu_clock / 2;
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/* change default value to udelay/mdelay take reasonable time */
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loops_per_jiffy = txx9_cpu_clock / HZ / 2;
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/* CCFG */
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/* enable Timeout BusError */
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if (txx9_ccfg_toeon)
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tx3927_ccfgptr->ccfg |= TX3927_CCFG_TOE;
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/* clear BusErrorOnWrite flag */
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tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_BEOW;
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if (read_c0_conf() & TX39_CONF_WBON)
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/* Disable PCI snoop */
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tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_PSNP;
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else
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/* Enable PCI SNOOP - with write through only */
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tx3927_ccfgptr->ccfg |= TX3927_CCFG_PSNP;
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/* do reset on watchdog */
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tx3927_ccfgptr->ccfg |= TX3927_CCFG_WR;
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printk(KERN_INFO "TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n",
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tx3927_ccfgptr->crir,
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tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg);
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/* TMR */
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for (i = 0; i < TX3927_NR_TMR; i++)
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txx9_tmr_init(TX3927_TMR_REG(i));
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/* DMA */
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tx3927_dmaptr->mcr = 0;
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for (i = 0; i < ARRAY_SIZE(tx3927_dmaptr->ch); i++) {
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/* reset channel */
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tx3927_dmaptr->ch[i].ccr = TX3927_DMA_CCR_CHRST;
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tx3927_dmaptr->ch[i].ccr = 0;
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}
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/* enable DMA */
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#ifdef __BIG_ENDIAN
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tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN;
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#else
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tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN | TX3927_DMA_MCR_LE;
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#endif
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/* PIO */
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__raw_writel(0, &tx3927_pioptr->maskcpu);
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__raw_writel(0, &tx3927_pioptr->maskext);
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txx9_gpio_init(TX3927_PIO_REG, 0, 16);
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conf = read_c0_conf();
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if (conf & TX39_CONF_DCE) {
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if (!(conf & TX39_CONF_WBON))
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pr_info("TX3927 D-Cache WriteThrough.\n");
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else if (!(conf & TX39_CONF_CWFON))
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pr_info("TX3927 D-Cache WriteBack.\n");
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else
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pr_info("TX3927 D-Cache WriteBack (CWF) .\n");
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}
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}
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void __init tx3927_time_init(unsigned int evt_tmrnr, unsigned int src_tmrnr)
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{
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txx9_clockevent_init(TX3927_TMR_REG(evt_tmrnr),
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TXX9_IRQ_BASE + TX3927_IR_TMR(evt_tmrnr),
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TXX9_IMCLK);
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txx9_clocksource_init(TX3927_TMR_REG(src_tmrnr), TXX9_IMCLK);
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}
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void __init tx3927_sio_init(unsigned int sclk, unsigned int cts_mask)
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{
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int i;
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for (i = 0; i < 2; i++)
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txx9_sio_init(TX3927_SIO_REG(i),
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TXX9_IRQ_BASE + TX3927_IR_SIO(i),
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i, sclk, (1 << i) & cts_mask);
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}
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void __init tx3927_mtd_init(int ch)
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{
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struct physmap_flash_data pdata = {
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.width = TX3927_ROMC_WIDTH(ch) / 8,
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};
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unsigned long start = txx9_ce_res[ch].start;
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unsigned long size = txx9_ce_res[ch].end - start + 1;
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if (!(tx3927_romcptr->cr[ch] & 0x8))
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return; /* disabled */
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txx9_physmap_flash_init(ch, start, size, &pdata);
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}
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