334 lines
6.9 KiB
C
334 lines
6.9 KiB
C
/*
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* Copyright (C) Freescale Semicondutor, Inc. 2006-2007. All rights reserved.
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*
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* Author: Andy Fleming <afleming@freescale.com>
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*
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* Based on 83xx/mpc8360e_pb.c by:
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* Li Yang <LeoLi@freescale.com>
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* Yin Olivia <Hong-hua.Yin@freescale.com>
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*
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* Description:
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* MPC85xx MDS board specific routines.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/reboot.h>
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#include <linux/pci.h>
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#include <linux/kdev_t.h>
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#include <linux/major.h>
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#include <linux/console.h>
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#include <linux/delay.h>
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#include <linux/seq_file.h>
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#include <linux/initrd.h>
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#include <linux/module.h>
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#include <linux/fsl_devices.h>
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#include <linux/of_platform.h>
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#include <linux/of_device.h>
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#include <linux/phy.h>
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#include <asm/system.h>
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#include <asm/atomic.h>
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#include <asm/time.h>
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#include <asm/io.h>
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#include <asm/machdep.h>
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#include <asm/pci-bridge.h>
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#include <asm/irq.h>
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#include <mm/mmu_decl.h>
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#include <asm/prom.h>
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#include <asm/udbg.h>
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#include <sysdev/fsl_soc.h>
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#include <sysdev/fsl_pci.h>
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#include <asm/qe.h>
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#include <asm/qe_ic.h>
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#include <asm/mpic.h>
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#undef DEBUG
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#ifdef DEBUG
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#define DBG(fmt...) udbg_printf(fmt)
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#else
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#define DBG(fmt...)
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#endif
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#define MV88E1111_SCR 0x10
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#define MV88E1111_SCR_125CLK 0x0010
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static int mpc8568_fixup_125_clock(struct phy_device *phydev)
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{
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int scr;
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int err;
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/* Workaround for the 125 CLK Toggle */
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scr = phy_read(phydev, MV88E1111_SCR);
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if (scr < 0)
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return scr;
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err = phy_write(phydev, MV88E1111_SCR, scr & ~(MV88E1111_SCR_125CLK));
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if (err)
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return err;
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err = phy_write(phydev, MII_BMCR, BMCR_RESET);
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if (err)
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return err;
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scr = phy_read(phydev, MV88E1111_SCR);
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if (scr < 0)
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return err;
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err = phy_write(phydev, MV88E1111_SCR, scr | 0x0008);
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return err;
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}
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static int mpc8568_mds_phy_fixups(struct phy_device *phydev)
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{
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int temp;
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int err;
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/* Errata */
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err = phy_write(phydev,29, 0x0006);
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if (err)
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return err;
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temp = phy_read(phydev, 30);
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if (temp < 0)
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return temp;
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temp = (temp & (~0x8000)) | 0x4000;
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err = phy_write(phydev,30, temp);
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if (err)
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return err;
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err = phy_write(phydev,29, 0x000a);
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if (err)
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return err;
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temp = phy_read(phydev, 30);
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if (temp < 0)
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return temp;
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temp = phy_read(phydev, 30);
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if (temp < 0)
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return temp;
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temp &= ~0x0020;
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err = phy_write(phydev,30,temp);
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if (err)
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return err;
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/* Disable automatic MDI/MDIX selection */
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temp = phy_read(phydev, 16);
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if (temp < 0)
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return temp;
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temp &= ~0x0060;
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err = phy_write(phydev,16,temp);
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return err;
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}
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/* ************************************************************************
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*
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* Setup the architecture
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*
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*/
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static void __init mpc85xx_mds_setup_arch(void)
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{
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struct device_node *np;
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static u8 __iomem *bcsr_regs = NULL;
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if (ppc_md.progress)
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ppc_md.progress("mpc85xx_mds_setup_arch()", 0);
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/* Map BCSR area */
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np = of_find_node_by_name(NULL, "bcsr");
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if (np != NULL) {
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struct resource res;
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of_address_to_resource(np, 0, &res);
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bcsr_regs = ioremap(res.start, res.end - res.start +1);
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of_node_put(np);
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}
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#ifdef CONFIG_PCI
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for_each_node_by_type(np, "pci") {
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if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
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of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
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struct resource rsrc;
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of_address_to_resource(np, 0, &rsrc);
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if ((rsrc.start & 0xfffff) == 0x8000)
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fsl_add_bridge(np, 1);
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else
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fsl_add_bridge(np, 0);
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}
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}
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#endif
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#ifdef CONFIG_QUICC_ENGINE
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np = of_find_compatible_node(NULL, NULL, "fsl,qe");
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if (!np) {
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np = of_find_node_by_name(NULL, "qe");
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if (!np)
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return;
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}
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qe_reset();
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of_node_put(np);
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np = of_find_node_by_name(NULL, "par_io");
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if (np) {
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struct device_node *ucc;
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par_io_init(np);
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of_node_put(np);
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for_each_node_by_name(ucc, "ucc")
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par_io_of_config(ucc);
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}
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if (bcsr_regs) {
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#define BCSR_UCC1_GETH_EN (0x1 << 7)
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#define BCSR_UCC2_GETH_EN (0x1 << 7)
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#define BCSR_UCC1_MODE_MSK (0x3 << 4)
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#define BCSR_UCC2_MODE_MSK (0x3 << 0)
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/* Turn off UCC1 & UCC2 */
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clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
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clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
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/* Mode is RGMII, all bits clear */
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clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK |
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BCSR_UCC2_MODE_MSK);
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/* Turn UCC1 & UCC2 on */
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setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
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setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
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iounmap(bcsr_regs);
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}
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#endif /* CONFIG_QUICC_ENGINE */
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}
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static int __init board_fixups(void)
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{
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char phy_id[BUS_ID_SIZE];
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char *compstrs[2] = {"fsl,gianfar-mdio", "fsl,ucc-mdio"};
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struct device_node *mdio;
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struct resource res;
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int i;
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for (i = 0; i < ARRAY_SIZE(compstrs); i++) {
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mdio = of_find_compatible_node(NULL, NULL, compstrs[i]);
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of_address_to_resource(mdio, 0, &res);
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snprintf(phy_id, BUS_ID_SIZE, "%x:%02x", res.start, 1);
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phy_register_fixup_for_id(phy_id, mpc8568_fixup_125_clock);
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phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);
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/* Register a workaround for errata */
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snprintf(phy_id, BUS_ID_SIZE, "%x:%02x", res.start, 7);
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phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);
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of_node_put(mdio);
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}
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return 0;
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}
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machine_arch_initcall(mpc85xx_mds, board_fixups);
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static struct of_device_id mpc85xx_ids[] = {
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{ .type = "soc", },
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{ .compatible = "soc", },
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{ .compatible = "simple-bus", },
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{ .type = "qe", },
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{ .compatible = "fsl,qe", },
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{},
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};
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static int __init mpc85xx_publish_devices(void)
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{
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/* Publish the QE devices */
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of_platform_bus_probe(NULL, mpc85xx_ids, NULL);
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return 0;
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}
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machine_device_initcall(mpc85xx_mds, mpc85xx_publish_devices);
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static void __init mpc85xx_mds_pic_init(void)
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{
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struct mpic *mpic;
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struct resource r;
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struct device_node *np = NULL;
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np = of_find_node_by_type(NULL, "open-pic");
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if (!np)
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return;
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if (of_address_to_resource(np, 0, &r)) {
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printk(KERN_ERR "Failed to map mpic register space\n");
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of_node_put(np);
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return;
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}
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mpic = mpic_alloc(np, r.start,
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MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
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0, 256, " OpenPIC ");
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BUG_ON(mpic == NULL);
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of_node_put(np);
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mpic_init(mpic);
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#ifdef CONFIG_QUICC_ENGINE
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np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
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if (!np) {
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np = of_find_node_by_type(NULL, "qeic");
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if (!np)
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return;
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}
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qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
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of_node_put(np);
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#endif /* CONFIG_QUICC_ENGINE */
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}
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static int __init mpc85xx_mds_probe(void)
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{
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unsigned long root = of_get_flat_dt_root();
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return of_flat_dt_is_compatible(root, "MPC85xxMDS");
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}
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define_machine(mpc85xx_mds) {
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.name = "MPC85xx MDS",
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.probe = mpc85xx_mds_probe,
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.setup_arch = mpc85xx_mds_setup_arch,
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.init_IRQ = mpc85xx_mds_pic_init,
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.get_irq = mpic_get_irq,
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.restart = fsl_rstcr_restart,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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#ifdef CONFIG_PCI
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.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
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#endif
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};
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