345 lines
8.9 KiB
C
345 lines
8.9 KiB
C
/* atomic.h: atomic operation emulation for FR-V
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*
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* For an explanation of how atomic ops work in this arch, see:
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* Documentation/fujitsu/frv/atomic-ops.txt
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*
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* Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef _ASM_ATOMIC_H
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#define _ASM_ATOMIC_H
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#include <linux/types.h>
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#include <asm/spr-regs.h>
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#ifdef CONFIG_SMP
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#error not SMP safe
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#endif
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/*
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* Atomic operations that C can't guarantee us. Useful for
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* resource counting etc..
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*
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* We do not have SMP systems, so we don't have to deal with that.
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*/
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/* Atomic operations are already serializing */
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#define smp_mb__before_atomic_dec() barrier()
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#define smp_mb__after_atomic_dec() barrier()
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#define smp_mb__before_atomic_inc() barrier()
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#define smp_mb__after_atomic_inc() barrier()
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typedef struct {
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int counter;
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} atomic_t;
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#define ATOMIC_INIT(i) { (i) }
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#define atomic_read(v) ((v)->counter)
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#define atomic_set(v, i) (((v)->counter) = (i))
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#ifndef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS
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static inline int atomic_add_return(int i, atomic_t *v)
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{
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unsigned long val;
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asm("0: \n"
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" orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */
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" ckeq icc3,cc7 \n"
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" ld.p %M0,%1 \n" /* LD.P/ORCR must be atomic */
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" orcr cc7,cc7,cc3 \n" /* set CC3 to true */
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" add%I2 %1,%2,%1 \n"
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" cst.p %1,%M0 ,cc3,#1 \n"
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" corcc gr29,gr29,gr0 ,cc3,#1 \n" /* clear ICC3.Z if store happens */
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" beq icc3,#0,0b \n"
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: "+U"(v->counter), "=&r"(val)
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: "NPr"(i)
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: "memory", "cc7", "cc3", "icc3"
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);
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return val;
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}
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static inline int atomic_sub_return(int i, atomic_t *v)
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{
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unsigned long val;
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asm("0: \n"
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" orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */
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" ckeq icc3,cc7 \n"
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" ld.p %M0,%1 \n" /* LD.P/ORCR must be atomic */
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" orcr cc7,cc7,cc3 \n" /* set CC3 to true */
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" sub%I2 %1,%2,%1 \n"
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" cst.p %1,%M0 ,cc3,#1 \n"
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" corcc gr29,gr29,gr0 ,cc3,#1 \n" /* clear ICC3.Z if store happens */
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" beq icc3,#0,0b \n"
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: "+U"(v->counter), "=&r"(val)
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: "NPr"(i)
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: "memory", "cc7", "cc3", "icc3"
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);
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return val;
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}
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#else
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extern int atomic_add_return(int i, atomic_t *v);
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extern int atomic_sub_return(int i, atomic_t *v);
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#endif
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static inline int atomic_add_negative(int i, atomic_t *v)
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{
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return atomic_add_return(i, v) < 0;
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}
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static inline void atomic_add(int i, atomic_t *v)
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{
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atomic_add_return(i, v);
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}
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static inline void atomic_sub(int i, atomic_t *v)
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{
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atomic_sub_return(i, v);
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}
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static inline void atomic_inc(atomic_t *v)
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{
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atomic_add_return(1, v);
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}
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static inline void atomic_dec(atomic_t *v)
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{
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atomic_sub_return(1, v);
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}
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#define atomic_dec_return(v) atomic_sub_return(1, (v))
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#define atomic_inc_return(v) atomic_add_return(1, (v))
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#define atomic_sub_and_test(i,v) (atomic_sub_return((i), (v)) == 0)
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#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0)
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#define atomic_inc_and_test(v) (atomic_add_return(1, (v)) == 0)
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#ifndef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS
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static inline
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unsigned long atomic_test_and_ANDNOT_mask(unsigned long mask, volatile unsigned long *v)
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{
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unsigned long old, tmp;
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asm volatile(
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"0: \n"
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" orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */
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" ckeq icc3,cc7 \n"
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" ld.p %M0,%1 \n" /* LD.P/ORCR are atomic */
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" orcr cc7,cc7,cc3 \n" /* set CC3 to true */
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" and%I3 %1,%3,%2 \n"
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" cst.p %2,%M0 ,cc3,#1 \n" /* if store happens... */
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" corcc gr29,gr29,gr0 ,cc3,#1 \n" /* ... clear ICC3.Z */
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" beq icc3,#0,0b \n"
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: "+U"(*v), "=&r"(old), "=r"(tmp)
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: "NPr"(~mask)
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: "memory", "cc7", "cc3", "icc3"
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);
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return old;
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}
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static inline
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unsigned long atomic_test_and_OR_mask(unsigned long mask, volatile unsigned long *v)
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{
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unsigned long old, tmp;
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asm volatile(
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"0: \n"
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" orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */
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" ckeq icc3,cc7 \n"
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" ld.p %M0,%1 \n" /* LD.P/ORCR are atomic */
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" orcr cc7,cc7,cc3 \n" /* set CC3 to true */
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" or%I3 %1,%3,%2 \n"
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" cst.p %2,%M0 ,cc3,#1 \n" /* if store happens... */
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" corcc gr29,gr29,gr0 ,cc3,#1 \n" /* ... clear ICC3.Z */
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" beq icc3,#0,0b \n"
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: "+U"(*v), "=&r"(old), "=r"(tmp)
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: "NPr"(mask)
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: "memory", "cc7", "cc3", "icc3"
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);
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return old;
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}
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static inline
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unsigned long atomic_test_and_XOR_mask(unsigned long mask, volatile unsigned long *v)
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{
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unsigned long old, tmp;
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asm volatile(
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"0: \n"
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" orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */
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" ckeq icc3,cc7 \n"
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" ld.p %M0,%1 \n" /* LD.P/ORCR are atomic */
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" orcr cc7,cc7,cc3 \n" /* set CC3 to true */
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" xor%I3 %1,%3,%2 \n"
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" cst.p %2,%M0 ,cc3,#1 \n" /* if store happens... */
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" corcc gr29,gr29,gr0 ,cc3,#1 \n" /* ... clear ICC3.Z */
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" beq icc3,#0,0b \n"
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: "+U"(*v), "=&r"(old), "=r"(tmp)
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: "NPr"(mask)
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: "memory", "cc7", "cc3", "icc3"
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);
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return old;
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}
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#else
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extern unsigned long atomic_test_and_ANDNOT_mask(unsigned long mask, volatile unsigned long *v);
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extern unsigned long atomic_test_and_OR_mask(unsigned long mask, volatile unsigned long *v);
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extern unsigned long atomic_test_and_XOR_mask(unsigned long mask, volatile unsigned long *v);
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#endif
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#define atomic_clear_mask(mask, v) atomic_test_and_ANDNOT_mask((mask), (v))
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#define atomic_set_mask(mask, v) atomic_test_and_OR_mask((mask), (v))
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/*****************************************************************************/
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/*
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* exchange value with memory
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*/
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#ifndef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS
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#define xchg(ptr, x) \
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({ \
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__typeof__(ptr) __xg_ptr = (ptr); \
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__typeof__(*(ptr)) __xg_orig; \
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\
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switch (sizeof(__xg_orig)) { \
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case 4: \
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asm volatile( \
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"swap%I0 %M0,%1" \
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: "+m"(*__xg_ptr), "=r"(__xg_orig) \
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: "1"(x) \
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: "memory" \
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); \
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break; \
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\
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default: \
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__xg_orig = (__typeof__(__xg_orig))0; \
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asm volatile("break"); \
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break; \
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} \
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\
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__xg_orig; \
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})
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#else
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extern uint32_t __xchg_32(uint32_t i, volatile void *v);
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#define xchg(ptr, x) \
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({ \
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__typeof__(ptr) __xg_ptr = (ptr); \
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__typeof__(*(ptr)) __xg_orig; \
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\
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switch (sizeof(__xg_orig)) { \
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case 4: __xg_orig = (__typeof__(*(ptr))) __xchg_32((uint32_t) x, __xg_ptr); break; \
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default: \
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__xg_orig = (__typeof__(__xg_orig))0; \
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asm volatile("break"); \
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break; \
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} \
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__xg_orig; \
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})
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#endif
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#define tas(ptr) (xchg((ptr), 1))
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/*****************************************************************************/
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/*
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* compare and conditionally exchange value with memory
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* - if (*ptr == test) then orig = *ptr; *ptr = test;
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* - if (*ptr != test) then orig = *ptr;
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*/
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#ifndef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS
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#define cmpxchg(ptr, test, new) \
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({ \
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__typeof__(ptr) __xg_ptr = (ptr); \
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__typeof__(*(ptr)) __xg_orig, __xg_tmp; \
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__typeof__(*(ptr)) __xg_test = (test); \
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__typeof__(*(ptr)) __xg_new = (new); \
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\
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switch (sizeof(__xg_orig)) { \
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case 4: \
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asm volatile( \
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"0: \n" \
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" orcc gr0,gr0,gr0,icc3 \n" \
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" ckeq icc3,cc7 \n" \
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" ld.p %M0,%1 \n" \
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" orcr cc7,cc7,cc3 \n" \
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" sub%I4cc %1,%4,%2,icc0 \n" \
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" bne icc0,#0,1f \n" \
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" cst.p %3,%M0 ,cc3,#1 \n" \
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" corcc gr29,gr29,gr0 ,cc3,#1 \n" \
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" beq icc3,#0,0b \n" \
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"1: \n" \
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: "+U"(*__xg_ptr), "=&r"(__xg_orig), "=&r"(__xg_tmp) \
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: "r"(__xg_new), "NPr"(__xg_test) \
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: "memory", "cc7", "cc3", "icc3", "icc0" \
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); \
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break; \
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\
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default: \
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__xg_orig = 0; \
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asm volatile("break"); \
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break; \
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} \
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\
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__xg_orig; \
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})
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#else
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extern uint32_t __cmpxchg_32(uint32_t *v, uint32_t test, uint32_t new);
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#define cmpxchg(ptr, test, new) \
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({ \
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__typeof__(ptr) __xg_ptr = (ptr); \
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__typeof__(*(ptr)) __xg_orig; \
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__typeof__(*(ptr)) __xg_test = (test); \
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__typeof__(*(ptr)) __xg_new = (new); \
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\
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switch (sizeof(__xg_orig)) { \
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case 4: __xg_orig = __cmpxchg_32(__xg_ptr, __xg_test, __xg_new); break; \
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default: \
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__xg_orig = 0; \
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asm volatile("break"); \
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break; \
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} \
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\
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__xg_orig; \
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})
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#endif
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#define atomic_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), old, new))
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#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
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#define atomic_add_unless(v, a, u) \
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({ \
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int c, old; \
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c = atomic_read(v); \
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while (c != (u) && (old = atomic_cmpxchg((v), c, c + (a))) != c) \
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c = old; \
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c != (u); \
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})
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#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
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#include <asm-generic/atomic.h>
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#endif /* _ASM_ATOMIC_H */
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