309 lines
8.6 KiB
C
309 lines
8.6 KiB
C
/*
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* BRIEF MODULE DESCRIPTION
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* ITE 8172G interrupt/setup routines.
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*
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* Copyright 2000,2001 MontaVista Software Inc.
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* Author: MontaVista Software, Inc.
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* ppopov@mvista.com or source@mvista.com
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*
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* Part of this file was derived from Carsten Langgaard's
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* arch/mips/mips-boards/atlas/atlas_int.c.
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*
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* Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/kernel_stat.h>
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#include <linux/module.h>
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/timex.h>
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#include <linux/slab.h>
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#include <linux/random.h>
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#include <linux/serial_reg.h>
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#include <linux/bitops.h>
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#include <asm/bootinfo.h>
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#include <asm/io.h>
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#include <asm/mipsregs.h>
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#include <asm/system.h>
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#include <asm/it8172/it8172.h>
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#include <asm/it8172/it8172_int.h>
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#include <asm/it8172/it8172_dbg.h>
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/* revisit */
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#define EXT_IRQ0_TO_IP 2 /* IP 2 */
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#define EXT_IRQ5_TO_IP 7 /* IP 7 */
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#define ALLINTS_NOTIMER (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
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extern void set_debug_traps(void);
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extern void mips_timer_interrupt(int irq, struct pt_regs *regs);
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struct it8172_intc_regs volatile *it8172_hw0_icregs =
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(struct it8172_intc_regs volatile *)(KSEG1ADDR(IT8172_PCI_IO_BASE + IT_INTC_BASE));
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static void disable_it8172_irq(unsigned int irq_nr)
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{
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if ( (irq_nr >= IT8172_LPC_IRQ_BASE) && (irq_nr <= IT8172_SERIRQ_15)) {
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/* LPC interrupt */
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it8172_hw0_icregs->lpc_mask |=
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(1 << (irq_nr - IT8172_LPC_IRQ_BASE));
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} else if ( (irq_nr >= IT8172_LB_IRQ_BASE) && (irq_nr <= IT8172_IOCHK_IRQ)) {
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/* Local Bus interrupt */
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it8172_hw0_icregs->lb_mask |=
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(1 << (irq_nr - IT8172_LB_IRQ_BASE));
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} else if ( (irq_nr >= IT8172_PCI_DEV_IRQ_BASE) && (irq_nr <= IT8172_DMA_IRQ)) {
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/* PCI and other interrupts */
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it8172_hw0_icregs->pci_mask |=
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(1 << (irq_nr - IT8172_PCI_DEV_IRQ_BASE));
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} else if ( (irq_nr >= IT8172_NMI_IRQ_BASE) && (irq_nr <= IT8172_POWER_NMI_IRQ)) {
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/* NMI interrupts */
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it8172_hw0_icregs->nmi_mask |=
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(1 << (irq_nr - IT8172_NMI_IRQ_BASE));
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} else {
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panic("disable_it8172_irq: bad irq %d", irq_nr);
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}
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}
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static void enable_it8172_irq(unsigned int irq_nr)
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{
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if ( (irq_nr >= IT8172_LPC_IRQ_BASE) && (irq_nr <= IT8172_SERIRQ_15)) {
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/* LPC interrupt */
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it8172_hw0_icregs->lpc_mask &=
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~(1 << (irq_nr - IT8172_LPC_IRQ_BASE));
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}
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else if ( (irq_nr >= IT8172_LB_IRQ_BASE) && (irq_nr <= IT8172_IOCHK_IRQ)) {
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/* Local Bus interrupt */
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it8172_hw0_icregs->lb_mask &=
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~(1 << (irq_nr - IT8172_LB_IRQ_BASE));
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}
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else if ( (irq_nr >= IT8172_PCI_DEV_IRQ_BASE) && (irq_nr <= IT8172_DMA_IRQ)) {
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/* PCI and other interrupts */
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it8172_hw0_icregs->pci_mask &=
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~(1 << (irq_nr - IT8172_PCI_DEV_IRQ_BASE));
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}
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else if ( (irq_nr >= IT8172_NMI_IRQ_BASE) && (irq_nr <= IT8172_POWER_NMI_IRQ)) {
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/* NMI interrupts */
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it8172_hw0_icregs->nmi_mask &=
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~(1 << (irq_nr - IT8172_NMI_IRQ_BASE));
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}
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else {
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panic("enable_it8172_irq: bad irq %d", irq_nr);
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}
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}
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static unsigned int startup_ite_irq(unsigned int irq)
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{
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enable_it8172_irq(irq);
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return 0;
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}
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#define shutdown_ite_irq disable_it8172_irq
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#define mask_and_ack_ite_irq disable_it8172_irq
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static void end_ite_irq(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
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enable_it8172_irq(irq);
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}
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static struct hw_interrupt_type it8172_irq_type = {
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.typename = "ITE8172",
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.startup = startup_ite_irq,
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.shutdown = shutdown_ite_irq,
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.enable = enable_it8172_irq,
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.disable = disable_it8172_irq,
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.ack = mask_and_ack_ite_irq,
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.end = end_ite_irq,
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};
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static void enable_none(unsigned int irq) { }
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static unsigned int startup_none(unsigned int irq) { return 0; }
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static void disable_none(unsigned int irq) { }
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static void ack_none(unsigned int irq) { }
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/* startup is the same as "enable", shutdown is same as "disable" */
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#define shutdown_none disable_none
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#define end_none enable_none
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static struct hw_interrupt_type cp0_irq_type = {
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.typename = "CP0 Count",
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.startup = startup_none,
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.shutdown = shutdown_none,
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.enable = enable_none,
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.disable = disable_none,
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.ack = ack_none,
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.end = end_none
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};
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void enable_cpu_timer(void)
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{
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unsigned long flags;
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local_irq_save(flags);
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set_c0_status(0x100 << EXT_IRQ5_TO_IP);
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local_irq_restore(flags);
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}
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void __init arch_init_irq(void)
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{
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int i;
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unsigned long flags;
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/* mask all interrupts */
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it8172_hw0_icregs->lb_mask = 0xffff;
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it8172_hw0_icregs->lpc_mask = 0xffff;
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it8172_hw0_icregs->pci_mask = 0xffff;
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it8172_hw0_icregs->nmi_mask = 0xffff;
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/* make all interrupts level triggered */
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it8172_hw0_icregs->lb_trigger = 0;
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it8172_hw0_icregs->lpc_trigger = 0;
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it8172_hw0_icregs->pci_trigger = 0;
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it8172_hw0_icregs->nmi_trigger = 0;
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/* active level setting */
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/* uart, keyboard, and mouse are active high */
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it8172_hw0_icregs->lpc_level = (0x10 | 0x2 | 0x1000);
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it8172_hw0_icregs->lb_level |= 0x20;
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/* keyboard and mouse are edge triggered */
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it8172_hw0_icregs->lpc_trigger |= (0x2 | 0x1000);
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#if 0
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// Enable this piece of code to make internal USB interrupt
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// edge triggered.
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it8172_hw0_icregs->pci_trigger |=
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(1 << (IT8172_USB_IRQ - IT8172_PCI_DEV_IRQ_BASE));
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it8172_hw0_icregs->pci_level &=
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~(1 << (IT8172_USB_IRQ - IT8172_PCI_DEV_IRQ_BASE));
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#endif
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for (i = 0; i <= IT8172_LAST_IRQ; i++) {
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irq_desc[i].handler = &it8172_irq_type;
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spin_lock_init(&irq_desc[i].lock);
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}
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irq_desc[MIPS_CPU_TIMER_IRQ].handler = &cp0_irq_type;
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set_c0_status(ALLINTS_NOTIMER);
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}
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void mips_spurious_interrupt(struct pt_regs *regs)
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{
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#if 1
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return;
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#else
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unsigned long status, cause;
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printk("got spurious interrupt\n");
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status = read_c0_status();
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cause = read_c0_cause();
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printk("status %x cause %x\n", status, cause);
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printk("epc %x badvaddr %x \n", regs->cp0_epc, regs->cp0_badvaddr);
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#endif
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}
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void it8172_hw0_irqdispatch(struct pt_regs *regs)
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{
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int irq;
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unsigned short intstatus = 0, status = 0;
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intstatus = it8172_hw0_icregs->intstatus;
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if (intstatus & 0x8) {
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panic("Got NMI interrupt");
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} else if (intstatus & 0x4) {
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/* PCI interrupt */
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irq = 0;
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status |= it8172_hw0_icregs->pci_req;
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while (!(status & 0x1)) {
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irq++;
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status >>= 1;
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}
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irq += IT8172_PCI_DEV_IRQ_BASE;
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} else if (intstatus & 0x1) {
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/* Local Bus interrupt */
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irq = 0;
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status |= it8172_hw0_icregs->lb_req;
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while (!(status & 0x1)) {
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irq++;
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status >>= 1;
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}
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irq += IT8172_LB_IRQ_BASE;
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} else if (intstatus & 0x2) {
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/* LPC interrupt */
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/* Since some lpc interrupts are edge triggered,
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* we could lose an interrupt this way because
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* we acknowledge all ints at onces. Revisit.
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*/
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status |= it8172_hw0_icregs->lpc_req;
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it8172_hw0_icregs->lpc_req = 0; /* acknowledge ints */
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irq = 0;
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while (!(status & 0x1)) {
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irq++;
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status >>= 1;
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}
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irq += IT8172_LPC_IRQ_BASE;
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} else
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return;
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do_IRQ(irq, regs);
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}
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asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
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{
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unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
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if (!pending)
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mips_spurious_interrupt(regs);
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else if (pending & CAUSEF_IP7)
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ll_timer_interrupt(127, regs);
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else if (pending & CAUSEF_IP2)
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it8172_hw0_irqdispatch(regs);
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}
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void show_pending_irqs(void)
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{
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fputs("intstatus: ");
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put32(it8172_hw0_icregs->intstatus);
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puts("");
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fputs("pci_req: ");
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put32(it8172_hw0_icregs->pci_req);
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puts("");
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fputs("lb_req: ");
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put32(it8172_hw0_icregs->lb_req);
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puts("");
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fputs("lpc_req: ");
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put32(it8172_hw0_icregs->lpc_req);
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puts("");
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}
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