79 lines
2.5 KiB
ArmAsm
79 lines
2.5 KiB
ArmAsm
#define VESTA
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#include "ppc_40x.h"
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#
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.align 2
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.text
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#
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# added by linguohui
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.extern initb_ebiu0, initb_config, hdw_init_finish
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.extern initb_hsmc0, initb_hsmc1, initb_cache
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# end added
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.globl HdwInit
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#
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HdwInit:
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#
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#-----------------------------------------------------------------------*
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# If we are not executing from the FLASH get out *
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#-----------------------------------------------------------------------*
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# SAW keep this or comment out a la Hawthorne?
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# r3 contains NIP when used with Linux
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# rlwinm r28, r3, 8, 24, 31 # if MSB == 0xFF -> FLASH address
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# cmpwi r28, 0xff
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# bne locn01
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#
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#
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#------------------------------------------------------------------------
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# Init_cpu. Bank registers are setup for the IBM STB.
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#------------------------------------------------------------------------
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#
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# Setup processor core clock to be driven off chip. This is GPI4 bit
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# twenty. Setup Open Drain, Output Select, Three-State Control, and
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# Three-State Select registers.
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#
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pb0pesr = 0x054
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pb0pear = 0x056
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mflr r30
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#-----------------------------------------------------------------------------
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# Vectors will be at 0x1F000000
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# Dummy Machine check handler just does RFI before true handler gets installed
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#-----------------------------------------------------------------------------
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#if 1 /* xuwentao added*/
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#ifdef SDRAM16MB
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lis r10,0x0000
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addi r10,r10,0x0000
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#else
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lis r10,0x1F00
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addi r10,r10,0x0000
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#endif
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mtspr evpr,r10 #EVPR: 0x0 or 0x1f000000 depending
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isync # on SDRAM memory model used.
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lis r10,0xFFFF # clear PB0_PESR because some
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ori r10,r10,0xFFFF # transitions from flash,changed by linguohui
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mtdcr pb0pesr,r10 # to load RAM image via RiscWatch
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lis r10,0x0000 # cause PB0_PESR machine checks
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mtdcr pb0pear,r10
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addis r10,r10,0x0000 # clear the
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mtxer r10 # XER just in case...
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#endif /* xuwentao*/
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bl initb_ebiu0 # init EBIU
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bl initb_config # config PPC and board
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#------------------------------------------------------------------------
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# EVPR setup moved to top of this function.
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#------------------------------------------------------------------------
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#
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mtlr r30
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blr
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.end
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